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* 8 AVR(R) * RISC
- 130 - - 32 8 - - 16 MHz 16 MIPS - * - 16K Flash : 10,000 - Boot Boot - 512 EEPROM : 100,000 - 1K SRAM
* * JTAG ( IEEE 1149.1 )
16KB Flash 8 ATmega169V ATmega169L ATmega169
*
*
* *
*
- JTAG - - JTAG Flash EEPROM - 4 x 25 LCD - 8 / - 16 / - RTC - PWM - 8 10 ADC - USART - / SPI - USI - - - MCU - (POR) (BOD) - RC - - ADC Standby I/O - 53 I/O - 64 TQFP 64 MLF : - ATmega169V1.8 - 5.5V - ATmega169L2.7 - 5.5V - ATmega1694.5 - 5.5V : - -40C 85C
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( )
* :
- ATmega169V 0 - 1 MHz - ATmega169L 0 - 8 MHz - ATmega169 0 - 16 MHz * - 1 MHz, 1.8V: 400A 32 kHz, 1.8V: 20A ( ) 32 kHz, 1.8V: 40A ( LCD) - : 1.8V 0.5A
Figure 1. ATmega169
PF6 (ADC6/TDO) PF5 (ADC5/TMS) PF4 (ADC4/TCK) PF7 (ADC7/TDI)
PA0 (COM0)
PA1 (COM1) 50
61
60
59
58
57
56
55
54
53
52
51
64
63
62
49
48 PA3 (COM3) 47 PA4 (SEG0) 46 PA5 (SEG1) 45 PA6 (SEG2) 44 PA7 (SEG3) 43 PG2 (SEG4) 42 PC7 (SEG5) 41 PC6 (SEG6) 40 PC5 (SEG7) 39 PC4 (SEG8) 38 PC3 (SEG9) 37 PC2 (SEG10) 36 PC1 (SEG11) 35 PC0 (SEG12) 34 33 PG1 (SEG13) PG0 (SEG14)
LCDCAP (RXD/PCINT0) PE0 (TXD/PCINT1) PE1 (XCK/AIN0/PCINT2) PE2 (AIN1/PCINT3) PE3 (USCK/SCL/PCINT4) PE4 (DI/SDA/PCINT5) PE5 (DO/PCINT6) PE6 (CLKO/PCINT7) PE7 (SS/PCINT8) PB0 (SCK/PCINT9) PB1 (MOSI/PCINT10) PB2 (MISO/PCINT11) PB3 (OC0A/PCINT12) PB4 (OC1A/PCINT13) PB5 (OC1B/PCINT14) PB6
1 2 INDEX CORNER 3 4 5 6 7 8 9 10 11 12 13 14 15 16
ATmega169
GND 22
(TOSC2) XTAL2 23
(TOSC1) XTAL1 24
(ICP1/SEG22) PD0 25
(INT0/SEG21) PD1 26
(SEG20) PD2 27
(SEG19) PD3 28
(OC2A/PCINT15) PB7 17
(T1/SEG24) PG3 18
(T0/SEG23) PG4 19
(SEG18) PD4 29
RESET 20
VCC 21
(SEG17) PD5 30
(SEG16) PD6 31
AVR
2
ATmega169V/L
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(SEG15) PD7 32
PA2 (COM2)
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
AVCC
AREF
GND
GND
VCC
ATmega169V/L
ATmega169 AVR RISC 8 CMOS ATmega169 1 MIPS/MHz
Figure 2.
PF0 - PF7
PA0 - PA7
PC0 - PC7
VCC GND PORTF DRIVERS PORTA DRIVERS PORTC DRIVERS
DATA REGISTER PORTF
DATA DIR. REG. PORTF
DATA REGISTER PORTA
DATA DIR. REG. PORTA
DATA REGISTER PORTC
DATA DIR. REG. PORTC
8-BIT DATA BUS
AVCC ADC AREF INTERNAL OSCILLATOR
CALIB. OSC
OSCILLATOR JTAG TAP PROGRAM COUNTER STACK POINTER WATCHDOG TIMER
TIMING AND CONTROL LCD CONTROLLER/ DRIVER
ON-CHIP DEBUG
PROGRAM FLASH
SRAM
MCU CONTROL REGISTER
BOUNDARYSCAN
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTERS
PROGRAMMING LOGIC
INSTRUCTION DECODER
INTERRUPT UNIT
RESET
CONTROL LINES
ALU
EEPROM
AVR CPU
STATUS REGISTER
USART
UNIVERSAL SERIAL INTERFACE
SPI
ANALOG COMPARATOR
DATA REGISTER PORTE
DATA DIR. REG. PORTE
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
DATA REG. PORTG
XTAL1
XTAL2
DATA DIR. REG. PORTG
+ -
PORTE DRIVERS
PORTB DRIVERS
PORTD DRIVERS
PORTG DRIVERS
PE0 - PE7
PB0 - PB7
PD0 - PD7
PG0 - PG4
3
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AVR 32 (ALU) CISC 10 ATmega169 :16K Flash( RWW) 512 EEPROM SRAM I/O 1K 53 32 JTAG LCD / (T/C), / USART 8 10 ADC SPI CPU SRAMT/CSPI LCD LCD ADC CPU LCD ADC I/O ADC Standby Atmel ISP Flash ISP AVR Flash(Application Flash Memory) FlashFlash(Boot Flash Memory) RWW 8 RISC CPU Flash ATmega169 ATmega169 C /
4
ATmega169V/L
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ATmega169V/L
VCC GND A (PA7..PA0) A 8 I/O A A P57 B (PB7..PB0) B 8 I/O B B B P58 C (PC7..PC0) C 8 I/O C C P61 D (PD7..PD0) D 8 I/O D D P63 E (PE7..PE0) E 8 I/O E E P65 F (PF7..PF0) F ADC ADC F 8 I/O F JTAG PF7(TDI) PF5(TMS) PF4(TCK) F JTAG G (PG4..PG0) G 5 I/O G G P67 RESET XTAL1 P37 Table 16
5
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XTAL2 AVCC AREF
AVCCFADC ADC VCC ADC VCC ADC C C
6
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ATmega169V/L
AVR CPU

AVR CPU Figure 3. AVR
Data Bus 8-bit
Flash Program Memory
Program Counter
Status and Control
Instruction Register
32 x 8 General Purpose Registrers
Interrupt Unit SPI Unit Watchdog Timer
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU
Control Lines
Analog Comparator
I/O Module1
Data SRAM
I/O Module 2
I/O Module n EEPROM
I/O Lines
AVR Harvard CPU ( ) FLASH 32 8 ALU ALU 6 3 16 16 X Y Z
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ALU ALU / 16 16 32 (Boot ) / SPM (PC) SRAM SRAM SP I/O SRAM 5 AVR AVR I/O I/O 64 CPU SPI I/O 0x20 - 0x5F ATmega169 SRAM 0x60 - 0xFF I/O I/O ST/STS/STD LD/LDS/LDD
ALU--
AVR ALU 32 ALU ALU 3 /
8
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ATmega169V/L
ALU AVR SREG
/ 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG
* 7 - I: I I I RETI I I SEI CLI * 6 - T: BLD BST T BST T BLD T * 5 - H: H BCD * 4 - S: S = N
V
S N 2 V * 3 - V: 2 2 * 2 - N: * * 1 - Z: * * 0 - C: *
AVR RISC / * * * * 8 8 8 8 8 16 16 16
Figure 4 CPU 32 9
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Figure 4. AVR CPU 32 x 8
7 R0 R1 R2 ... R13 R14 R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X X Y Y Z Z 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02
Figure 4 32 SRAM X Y Z
10
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XYZ R26..R31 Figure 5 Figure 5. X Y Z
15 X 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0
15 Y 7 R29 (0x1D) 15 Z 7 R31 (0x1F)
YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E)
YL
0 0
ZL 0
0

/ AVR SRAM 0xFF PUSH POP RET RETI AVRI/O8 AVR SPL SPH
15 SP15 SP7 7 / R/W R/W 0 0 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL
11
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AVR CPU clkCPU Figure 6 Harvard 1 MIPS/MHz / / Figure 6.
T1 T2 T3 T4
clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch
Figure 7 ALU Figure 7. ALU
T1 T2 T3 T4
clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back
AVR I PC BLB02 BLB12 P256 " " P45 "" RESET INT0 - 0 MCU (MCUCR) IVSEL Flash BOOTRST Flash P243 "Boot Loader - RWW " I I RETI I "1" "0"
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ATmega169V/L
I AVR CLI CLI CLI EEPROM EEPROM
in cli r16, SREG ; ; EEPROM ; SREG (I ) ; SREG
sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16
C
char cSREG; cSREG = SREG; /* */ _CLI(); EECR |= (1<13
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SEI .
sei ; sleep ; ; : MCU
C
_SEI(); /* */ _SLEEP(); /* */ /* : MCU */
AVR 4 4 4 PC 3 MCU MCU 4 4 PC( ) SREG I
14
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ATmega169V/L
AVR ATmega169
ATmega169 AVR ATmega169 EEPROM
Flash ATmega16916KFlash AVR 16 32 Flash 8K x 16 Flash
(Boot) Flash 10,000 ATmega169 (PC) 13 8K P243 "Boot Loader - RWW " P256 " " SPI JTAG Flash ( LPM ) P12 " " Figure 8.
Program Memory 0x0000
Application Flash Section
Boot Flash Section 0x1FFF
SRAM
Figure 9 ATmega169 SRAM ATmega169 64I/O(IN/OUT ) I/O 0x60 - 0xFF ST/STS/STD LD/LDS/LDD
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1,280 I/O I/O SRAM 32 64 I/O 160 I/O 1024 SRAM 5 R26 R31 Y Z 63 X Y Z ATmega16932 64I/O 160I/O1024 SRAM P9 " " Figure 9.
Data Memory
32 Registers 64 I/O Registers 160 Ext I/O Reg. Internal SRAM (1024 x 8) 0x04FF 0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF 0x0100
16
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ATmega169V/L
Figure 10 SRAM clkCPU Figure 10. SRAM
T1 T2 T3
clkCPU Address Data WR Data RD
Compute Address Address valid
Memory Access Instruction
Next Instruction
EEPROM
ATmega169 512 EEPROM EEPROM 100,000 EEPROM SPIJTAGEEPROMP269P274 P259
EEPROM /
EEPROM I/O EEPROM Table 1 EEPROM / VCC / CPU P21 " EEPROM " EEPROM EEPROM EEPROM EEPROM CPU 4 EEPROM CPU 2
Read
Write
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EEPROM --EEARH EEARL
15 - EEAR7 7
14 - EEAR6 6 R R/W 0 X
13 - EEAR5 5 R R/W 0 X
12 - EEAR4 4 R R/W 0 X
11 - EEAR3 3 R R/W 0 X
10 - EEAR2 2 R R/W 0 X
9 - EEAR1 1 R R/W 0 X
8 EEAR8 EEAR0 0 R/W R/W X X EEARH EEARL
/
R R/W 0 X
* 15..9 - Res: * 8..0 - EEAR8..0: EEPROM EEPROM- EEARHEEARL512EEPROM EEPROM 0 511EEAR EEPROM EEPROM --EEDR
/ 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 EEDR
* 7..0 - EEDR7..0: EEPROM EEPROM EEDR EEAR EEDR EEAR EEPROM --EECR
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 EERIE R/W 0 2 EEMWE R/W 0 1 EEWE R/W X 0 EERE R/W 0 EECR
* 7..4 - Res: * 3 - EERIE: EEPROM SREG I "1" EERIE EEPROM EERIE EEWE EEPROM * 2 - EEMWE: EEPROM EEMWEEEWEEEPROM EEMWE"1" 4 EEWE EEPROM EEMWE "0" EEWE EEMWE 4 EEPROM EEWE * 1 - EEWE: EEPROM EEWE EEPROM EEPROM EEWE EEPROM EEMWE EEPROM ( 3 4 ) 18
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ATmega169V/L
1. EEWE 2. SPMCSR SPMEN 3. EEPROM EEAR( ) 4. EEPROM EEDR( ) 5. EECR EEMWE "1" EEWE 6. EEMWE 4 EEWE CPU Flash EEPROM EEPROM Flash (2) CPU Flash CPU Flash (2) P243 "Boot Loader - RWW " 5 6 EEPROM EEPROM EEPROM EEAR EEDR EEPROM I EEWE EEWE CPU * 0 - EERE: EEPROM EEREEEPROM EEPROM EERE EEAR EEPROM EEPROM CPU 4 EEPROM EEWE EEPROM EEAR EEPROM Table 1 CPU EEPROM . Table 1. EEPROM
EEPROM (CPU) RC (1) 67 584 8.5 ms
19
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C EEPROM Boot Loader Boot Loader EEPROM SPM .
EEPROM_write: ; W sbic EECR,EEWE rjmp EEPROM_write ; (r18:r17) out out out sbi sbi ret EEARH, r18 EEARL, r17 EEDR,r16 EECR,EEMWE EECR,EEWE
; (r16) ; EEMWE ; EEWE
C
void EEPROM_write(unsigned int uiAddress, unsigned char ucData) { /* */ while(EECR & (1<20
ATmega169V/L
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ATmega169V/L
C EEPROM
EEPROM_read: ; sbic EECR,EEWE rjmp EEPROM_read ; (r18:r17) out out sbi in ret EEARH, r18 EEARL, r17 EECR,EERE r16,EEDR
; EERE ;
C
unsigned char EEPROM_read(unsigned int uiAddress) { /* */ while(EECR & (1< EEPROM EEPROM
EEPROM EEPROM EEPROM CPU EEPROM EEPROM ( ) EEPROM EEPROM EEPROM CPU EEPROM AVR RESET BOD BOD
I/O
.ATmega169 I/O P325 " " ATmega169 I/O I/O I/O LD/LDS/LDD ST/STS/STD 32 I/O 0x00 - 0x1F I/O SBI CBI SBIS SBIC IN OUT 21
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0x00 - 0x3F SRAMLDSTI/O 0x20 ATmega169 64 I/O( IN/OUT ) I/O 0x60 - 0xFF ST/STS/STD LD/LDS/LDD "0" I/O "1" AVR CBI SBI CBI SBI 0x00 0x1F I/O I/O ATmega169 3 I/O 0x00 - 0x1F I/O SBI CBI SBIS SBIC
/ 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 GPIOR2
I/O 2--GPIOR2
I/O 1--GPIOR1
/
7 MSB R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 LSB R/W 0 GPIOR1
I/O 0--GPIOR0
/
7 MSB R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 LSB R/W 0 GPIOR0
22
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ATmega169V/L
Figure 11AVR P32 " " Figure 11.
LCD Controller Asynchronous Timer/Counter General I/O Modules CPU Core RAM Flash and EEPROM
clkI/O clkASY
AVR Clock Control Unit
clkCPU clkFLASH
Reset Logic
Watchdog Timer
Source clock System Clock Prescaler
Watchdog clock
Oscillator Watchdog
Clock Multiplexer
Timer/Counter Oscillator
External Clock
Crystal Oscillator
Low-frequency Crystal Oscillator
Calibrated RC Oscillator
CPU --clkCPU I/O --clkI/O
CPUAVR CPU I/O I/O / SPI USART I/O I/O USI clkI/O Flash Flash CPU / LCD 32 kHz / LCD ADC ADCCPUI/O ADC
Flash --clkFLASH --clkASY
ADC --clkADC
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ATmega169Flash AVR . Table 2. (1)
/ RC "1" "0" CKSEL3..0 1111 - 1000 0111 - 0100 0010 0000 0011, 0001
CPU CPU MCU WDT Table 3 P292 "ATmega169 - " Table 3.
(VCC = 5.0V) 4.1 ms 65 ms (VCC = 3.0V) 4.3 ms 69 ms 4K (4,096) 64K (65,536)
CKSEL = "0010" SUT = "10" CKDIV8 RC 8 ISP
24
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ATmega169V/L
XTAL1 XTAL2 Figure 12 C1 C2 Table 4 Figure 12.
C2 C1
XTAL2 XTAL1 GND
CKSEL3..1 Table 4 Table 4.
CKSEL3..1 100(1) 101 110 111 Notes: (MHz) 0.4 - 0.9 0.9 - 3.0 3.0 - 8.0 8.0 1. C1 C2 (pF) - 12 - 22 12 - 22 12 - 22
Table 5 CKSEL0 SUT1..0
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Table 5.
CKSEL0 0 0 0 0 1 SUT1..0 00 01 10 11 00 01 10 11 258 CK
(1)
(VCC = 5.0V) 14CK + 4.1 ms 14CK + 65 ms 14CK 14CK + 4.1 ms 14CK + 65 ms 14CK 14CK + 4.1 ms 14CK + 65 ms
BOD BOD
258 CK(1) 1K CK(2) 1K CK(2) 1K CK(2) 16K CK 16K CK 16K CK
1 1 1 Notes:
1. 2.
32.768 kHz CKSEL "0100" "0101" "0110" "0111" Figure 12 SUT(Table 6 ) CKSEL1..0(Table 7 ) Table 6.
SUT1..0 00 01 10 11 (VCC = 5.0V) 14CK 14CK + 4.1 ms 14CK + 65 ms BOD
26
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ATmega169V/L
Table 7.
CKSEL3..0 0100
(1)
1K CK 32K CK 1K CK 32K CK

0101 0110(1) 0111 Note:
1.
RC
RC 8.0 MHz , 3V 25C 8 MHz ( VCC ) CKDIV8 8 CKDIV8 P30 " " Table 8 CKSEL OSCCAL RC 3V 25C 1% P259 " " Table 8. I RC
CKSEL3..0 0010 Note: 1. 8.0 MHz
SUT Table 9 RC XTAL1/TOSC1 XTAL2/TOSC2 . Table 9. RC
SUT1..0 00 01 10
(1)
6 CK 6 CK 6 CK
(VCC = 5.0V) 14CK 14CK + 4.1 ms 14CK + 65 ms
BOD
11 Note: 1.
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--OSCCAL
/
7 - R
6 CAL6 R/W
5 CAL5 R/W
4 CAL4 R/W
3 CAL3 R/W
2 CAL2 R/W
1 CAL1 R/W
0 CAL0 R/W OSCCAL
* 6..0 - CAL6..0: OSCCAL 0x7F EEPROM Flash EEPROM Flash 10% 8.0 MHz Table 10 . Table 10. RC
OSCCAL 0x00 0x3F 0x7F ( ) 50% 75% 100% ( ) 100% 150% 200%
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ATmega169V/L
XTAL1 Figure 13 CKSEL "0000" Figure 13.
NC
XTAL2
EXTERNAL CLOCK SIGNAL
XTAL1
GND
SUT Table 12 . Table 11.
CKSEL3..0 0000 0 - 16 MHz
Table 12.
SUT1..0 00 01 10 11 6 CK 6 CK 6 CK (VCC = 5.0V) 14CK 14CK + 4.1 ms 14CK + 65 ms BOD
MCU 2% MCU P30 " "
CKOUT CLKO CKOUT I/O CLKO RC
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/
ATmega169 /TOSC1/TOSC2XTAL1 /XTAL2 RC / 32.768 kHz P25 Figure 12 ASSR EXTCLK "1" TOSC1 32 kHz P131 " / "
ATmega169CLKPR CPU clkI/O clkADC clkCPU clkFLASH Table 13
/ 7
CLKPCE
--CLKPR
6
-
5
-
4
-
3
CLKPS3
2
CLKPS2
1
CLKPS1
0
CLKPS0 CLKPR
R/W 0
R 0
R 0
R 0
R/W
R/W
R/W
R/W
* 7 - CLKPCE: CLKPS CLKPCE "1" CLKPR "0" CLKPCE CLKPCE "1" 4 CLKPS 4 CLKPCE 4 CLKPCE CLKPCE * 3..0 - CLKPS3..0: 3 - 0 MCU Table 13 CLKPS 1. (CLKPCE) CLKPR 2. 4 CLKPS CLKPCE CKDIV8 CLKPS CKDIV8 CLKPS "0000" CKDIV8 CLKPS"0011" 8 CKDIV8 CLKPS CKDIV8 Table 13.
CLKPS3 0 0 0 0 0 0 0 CLKPS2 0 0 0 0 1 1 1 CLKPS1 0 0 1 1 0 0 1 CLKPS0 0 1 0 1 0 1 0 1 2 4 8 16 32 64
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Table 13.
CLKPS3 0 1 1 1 1 1 1 1 1 CLKPS2 1 0 0 0 0 1 1 1 1 CLKPS1 1 0 0 1 1 0 0 1 1 CLKPS0 1 0 1 0 1 0 1 0 1 128 256
CPU CLKPS T1 + T2 T1 + 2*T2 2 T1 T2
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MCU AVR 5 MCUCR SE SLEEP ( ADC Standby ) MCUCR SM2 SM1 SM0 Table 14 MCU 4 ( MCU ) MCU MCU SLEEP SRAM MCU P23 Figure 11 ATmega169
--SMCR
.
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 SM2 R/W 0 2 SM1 R/W 0 1 SM0 R/W 0 0 SE R/W 0 SMCR
* 3 2 1 - SM2..0: 2 1 0 Table 14 Table 14.
SM2 0 0 0 0 1 1 1 1 Note: SM1 0 0 1 1 0 0 1 1 SM0 0 1 0 1 0 1 0 1 ADC Standby
1. Standby
* 1 - SE: MCU SLEEP SE SLEEP SEMCU SE
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SM2..0 000 SLEEP MCU CPU LCD SPI USART ADC USI / clkCPU clkFLASH USART MCU MCU ACSR ACD ADC
ADC
SM2..0 001 SLEEP MCU CPU ADC USI / 2 LCD ( ) clkI/O CPU clkFLASH clk ADC ADC AD ADC BOD LCD USI / 2 SPM/EEPROM INT0 MCU ADC
SM2..0 010 SLEEP MCU USI ( ) BOD USI INT0 MCU MCU P74 " " CKSEL P24 " "
SM2..0 011 SLEEP MCU / 2 / LCD / 2 MCU TIMSK2 SREG I LCD MCU / 2 LCD / 2 LCD LCD / 2 / LCD / 2 LCD / 2
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Standby
SM2..0 110 SLEEP MCU Standby 6
Table 15. MCU
X X X(2) X(2)
INT0 USI
LCD
ADC
clkCPU clkFLASH clkIO clkADC clkASY
EEPROM 2 ADC X X(2) X X X X
SPM/
I/O
X
X X
X X
X X(3) X
(3) (3)
X X X X X
X X(2)
X
X
X
X
X
X
Standby X Notes: 1. 2. LCD / 2 3. INT0
X(3)
AVR ADC ADC P184 " " ADC P181 " " BOD BODEN BOD P39" " BOD BOD ADC P41" " P42 " " I/O clkI/O ADC clkADC P54 " " VCC/2

BOD
34
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ATmega169V/L
VCC/2 (DIDR1 DIDR0) P183 " 1 - DIDR1" P201 " 0 - DIDR0" JTAG OCDEN * * * OCDEN JTAGEN MCUCSR JTD
JTAG JTAG TAP TDO TDO TDI TDO MCUCSR JTD JTAG JTAG
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AVR I/O JMP Boot -- -- Figure 14 Table 16 I/O MCU SUT CKSEL P24 " " ATmega169 5 * * * * * VPOT MCU RESET MCU VBOT MCU JTAG AVR 1 MCU P224 "IEEE 1149.1 (JTAG) "
Figure 14.
DATA BUS
MCU Status Register (MCUSR)
PORF BORF EXTRF WDRF JTRF
Power-on Reset Circuit
BODLEVEL [2..0] Pull-up Resistor
SPIKE FILTER
Brown-out Reset Circuit
JTAG Reset Register
Watchdog Oscillator
Clock Generator
CK
Delay Counters TIMEOUT
CKSEL[3:0] SUT[1:0]
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Table 16.
( ) ( )(1) RESET RESET TA = -40C 85C TA = -40C 85C VCC = 3V VCC = 3V 0.7 0.6 0.1 VCC 1.0 0.9 1.4 1.3 0.9 VCC 2.5 V V V s
VPOT
VRST tRST Notes:
1. VPOT
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(POR) Table 16 VCC POR POR POR CC V VCC RESET Figure 15. MCU RESET VCC
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
Figure 16. MCU RESET
VCC VPOT
RESET
VRST
TIME-OUT
tTOUT
INTERNAL RESET
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ATmega169V/L
RESET ( Table 16) VRST( ) tTOUT MCU Figure 17.
CC
ATmega169 BOD(Brown-out Detection) VCC BODLEVEL BOD VBOT+ = VBOT + VHYST/2 VBOT- = VBOT - VHYST/2 Table 17. BODLEVEL (1)
BODLEVEL 2..0 111 110 101 100 011 010 001 000 Note: 1. VBOT VCC VCC = VBOT ATmega169VBODLEVEL = 110 ATmega169L BODLEVEL = 101 1.5 2.4 4.0 VBOT VBOT 1.8 2.7 4.5 VBOT 2.1 3.0 4.6 V BOD
Table 18.
VHYST tBOD 50 2 mV s
BOD VCC (VBOT- Figure 18) BOD VCC (VBOT+ Figure 18) tTOUT MCU
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2514I-AVR-10/03
VCC Table 16 tBOD BOD Figure 18.
VCC VBOTVBOT+
RESET
TIME-OUT
tTOUT
INTERNAL RESET
1 CK tTOUT P42 Figure 19.
CC
CK
MCU --MCUCSR
MCU MCU
/ 7 - R 0 6 - R 0 5 - R 0 4 JTRF R/W 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR
* 4 - JTRF: JTAG JTAG AVR_RESET JTAG MCU JTRF "0" * 3 - WDRF: "0" * 2 - BORF: "0"
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ATmega169V/L
* 1 - EXTRF: "0" * 0 - PORF: "0" MCUSR
ATmega169 ADC Table 19 1. BOD ( BODLEVEL [2..0] ) 2. (ACSR ACBG ) 3. ADC BOD ACBG ADC Table 19. (1)
VBG tBG IBG Note: 1. VCC = 2.7V, TA = 25C VCC = 2.7V, TA = 25C VCC = 2.7V, TA = 25C 1.05 1.1 40 15 1.35 70 V s A
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1 Mhz VCC = 5V VCC P43 Table 21 WDR 8 ATmega169 P43 Table 21 WDTON 2 Table 20. P44 " " Table 20. WDTON WDT
WDTON 1 2 WDT WDT
Figure 20.
WATCHDOG OSCILLATOR
-- WDTCR
/
7 - R 0
6 - R 0
5 - R 0
4 WDCE R/W 0
3 WDE R/W 0
2 WDP2 R/W 0
1 WDP1 R/W 0
0 WDP0 R/W 0 WDTCR
* 7..5 - Res: ATmega169 * 4 - WDCE: WDE WDCE 4 WDE WDCE P44 " " * 3 - WDE: WDE"1" WDCE"1"WDE 1. WDCE WDE "1" WDE "1" 2. 4 WDE "0"
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2 P44 " " * 2..0 - WDP2, WDP1, WDP0: 2, 1 0 WDP2 WDP1 WDP0 Table 21 . Table 21.
WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 16K 32K 64K 128K 256K 512K 1,024K 2,048K VCC = 3.0V 17.1 ms 34.3 ms 68.5 ms 0.14 s 0.27 s 0.55 s 1.1 s 2.2 s VCC = 5.0V 16.3 ms 32.5 ms 65 ms 0.13 s 0.26 s 0.52 s 1.0 s 2.1 s
C WDT ( )
WDT_off: ; WDT wdr ; WDCE WDE in ori out ldi out ret r16, WDTCR r16, (1<; WDT
C (1)
void WDT_off(void) { /* WDT */ _WDR; /* W WDCE WDE*/ WDTCR |= (1<Note:
1. I/OI/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
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1 WDE ( ) 1. WDCE WDE "1" WDE "1" 2. 4 WDE WDP WDCE "0" 2 WDE "1" 1. WDCEWDE"1" WDE "1" 2. 4 WDCE "0" WDP WDE
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ATmega169
ATmega169 AVRP12"" Table 22.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Notes: (2) 0x0000
(1)
RESET INT0 PCINT0 PCINT1 TIMER2 COMP TIMER2 OVF TIMER1 CAPT TIMER1 COMPA TIMER1 COMPB TIMER1 OVF TIMER0 COMP TIMER0 OVF SPI, STC USART, RX USART, UDRE USART, TX USI START USI OVERFLOW ANALOG COMP ADC EE READY SPM READY LCD
JTAG AVR 0 0 1 / 2 / 2 / 1 / 1 A / 1 B / 1 / 0 / 0 SPI USART Rx USART USART Tx USI USI ADC EEPROM LCD (SOF)
0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C
1. BOOTRST MCUBoot Loader P243 "Boot Loader - RWW " 2. MCUCRIVSEL Boot Boot
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Table 23 BOOTRST/IVSEL Boot Table 23.
BOOTRST 1 1 0 0 Note: IVSEL 0 1 0 1 0x0000 0x0000 Boot Boot 0x0002 Boot + 0x0002 0x0002 Boot + 0x0002
1. Boot P253 Table 113 BOOTRST "0" "1"
jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp jmp RESET: ldi out ldi out sei ... ... ; ; IRQ0 ; PCINT0 ; PCINT0 ; 2 ; 2 ; 1 ; 1 A ; 1 B ; 1 ; 0 ; 0 ; SPI ; USART RX ; USART,UDR ; USART TX ; USI ; USI ; ; ADC ; EEPROM ; SPM ; LCD
ATmega169
0x0000 0x0002 0x0004 0x0006 0x0008 0x000A 0x000C 0x000E 0x0010 0x0012 0x0014 0x0016 0x0018 0x001A 0x001C 0x001E 0x0020 0x0022 0x0024 0x0026 0x0028 0x002A 0x002C ; 0x002E 0x002F 0x0030 0x0031 0x0032 0x0033 ... RESET EXT_INT0 PCINT0 PCINT1 TIM2_COMP TIM2_OVF TIM1_CAPT TIM1_COMPA TIM1_COMPB TIM1_OVF TIM0_COMP TIM0_OVF SPI_STC USART_RXC USART_DRE USART_TXC USI_STRT USI_OVFL ANA_COMP ADC EE_RDY SPM_RDY LCD_SOF
r16, high(RAMEND); SPH,r16 r16, low(RAMEND) SPL,r16 ; xxx ... RAM
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BOOTRST Boot 2K MCUCR IVSEL
0x0000 0x0001 0x0002 0x0003 0x0004 0x0005 ; .org 0x1C02 0x1C02 0x1C04 ... 0x1C2C jmp jmp ... jmp EXT_INT0 PCINT0 ... SPM_RDY ; IRQ0 ; PCINT0 ; ; SPM RESET: ldi out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM
BOOTRST Boot 2K
.org 0x0002 0x0002 0x0004 ... 0x002C ; .org 0x1C00 0x1C00 RESET: ldi 0x1C01 0x1C02 0x1C03 0x1C04 0x1C05 out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM jmp jmp ... jmp EXT_INT0 PCINT0 ... SPM_RDY ; IRQ0 ; PCINT0 ; ; SPM
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BOOTRST Boot 2K MCUCR IVSEL
; .org 0x1C00 0x1C00 0x1C02 0x1C04 ... 0x1C2C ; 0x1C2E 0x1C2F 0x1C30 0x1C31 0x1C32 0x1C33 RESET: ldi out ldi out sei r16,high(RAMEND) ; SPH,r16 r16,low(RAMEND) SPL,r16 ; xxx ; RAM jmp jmp jmp ... jmp RESET EXT_INT0 PCINT0 ... SPM_RDY ; Reset ; IRQ0 ; PCINT0 ; ; SPM
Boot MCU --MCUCR
/
7 JTD R/W 0
6 - R 0
5 - R 0
4 PUD R/W 0
3 - R 0
2 - R 0
1 IVSEL R/W 0
0 IVCE R/W 0 MCUCR
* 1 - IVSEL: IVSEL "0" Flash IVSEL "1" Boot Boot BOOTSZ P243 "Boot Loader - RWW " IVSEL 1. IVCE 2. 4 IVSEL IVCE "0" IVCE IVSEL IVSEL IVCE 4 I
Note: Boot BootBLB02 Boot BLB12 Boot Boot P243 "Boot Loader - RWW "
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* 0 - IVCE: IVSEL IVCE IVCE IVSEL 4 IVCE IVCE
Move_interrupts: ; ldi out ldi out ret r16, (1<; boot
C
void Move_interrupts(void) { /* */ MCUCR = (1<49
2514I-AVR-10/03
I/O
I/O AVR I/O - - SBI CBI ( / ) ( / ) LED VCC Figure 21 P286 " " Figure 21. I/O
Rpu
Pxn
Logic Cpin
See Figure "General Digital I/O" for Details
: "x" "n" PORTB3 B 3 PORTxn I/O P71 "I/O " I/O : - PORTx - DDRx - PINx / PINx "1" "0" "1" MCUCR PUD I/O P50 " I/O " P55 " " I/O
I/O
I/O Figure 22 I/O
50
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ATmega169V/L
Figure 22. I/O(1)
PUD
Q
D
DDxn Q CLR
RESET
WDx RDx
1 Pxn
Q D PORTxn Q CLR
0
RESET SLEEP RRx
WPx WRx
SYNCHRONIZER
D Q D Q
RPx
PINxn L Q Q
clk I/O
PUD: SLEEP: clkI/O:
PULLUP DISABLE SLEEP CONTROL I/O CLOCK
WDx: RDx: WRx: RRx: RPx: WPx:
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER
Note:
1. WRx, WPx, WDx, RRx, RPx RDx clkI/O, SLEEP PUD
: DDxn PORTxn PINxn P71 "I/O " DDxn DDRx PORTxn PORTx PINxn PINx DDxn DDxn "1" Pxn PORTxn "1" PORTxn PORTxn "1" ("1") ("0")

DDRxn PINxn " 1" PORTxn "0" "1" SBI ( )({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b11) ({DDxn, PORTxn} = 0b01) ({DDxn, PORTxn} = 0b10) SFIOR PUD ({DDxn, PORTxn} = 0b00) ({DDxn, PORTxn} = 0b10)
DATA BUS
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Table 24 Table 24.
DDxn 0 0 0 1 1 PORTxn 0 1 1 0 1 PUD( MCUCR) X 0 1 X X I/O No Yes No No No (Hi-Z) (Hi-Z) ( ) ( )
DDxn PINxn Figure 22 PINxn Figure 23 tpd,max tpd,min Figure 23.
SYSTEM CLK INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd, max t pd, min 0xFF XXX XXX in r17, PINx
SYNC LATCH PINxn pd,max tpd,min t 1/2 11/2 Figure 24. out in nop out SYNC LATCH tpd
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ATmega169V/L
Figure 24.
SYSTEM CLK r16 INSTRUCTIONS SYNC LATCH PINxn r17
0x00 t pd 0xFF out PORTx, r16 nop 0xFF in r17, PINx
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B 0 1 2 3 4 7 6 7 nop (1)
... ; ; ldi ldi out out nop ; in ... r16,PINB r16,(1<; nop
C
unsigned char i; ... /* */ /* */ PORTB = (1<Note:
1.
Figure 22 ( ) SLEEP MCU Standby VCC/2 SLEEP SLEEP SLEEP P55 " " ("1") " " "1" "0" "0" "1"
( )
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VCC GND
I/O Figure 25 Figure 22 AVR Figure 25. (1)
PUOExn PUOVxn
1 0
PUD
DDOExn DDOVxn
1 0
QD DDxn Q CLR
PVOExn PVOVxn
WDx RESET RDx
1 Pxn 0
Q D
1 0
PORTxn
PTOExn WPx WRx RRx
DIEOExn DIEOVxn
1 0
Q CLR
RESET
SLEEP SYNCHRONIZER
D
SET
RPx
Q
D
Q
PINxn L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: DIEOVxn: SLEEP: PTOExn:
Pxn PULL-UP OVERRIDE ENABLE Pxn PULL-UP OVERRIDE VALUE Pxn DATA DIRECTION OVERRIDE ENABLE Pxn DATA DIRECTION OVERRIDE VALUE Pxn PORT VALUE OVERRIDE ENABLE Pxn PORT VALUE OVERRIDE VALUE Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP CONTROL Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD: WDx: RDx: RRx: WRx: RPx: WPx: clkI/O: DIxn: AIOxn:
PULLUP DISABLE WRITE DDRx READ DDRx READ PORTx REGISTER WRITE PORTx READ PORTx PIN WRITE PINx I/O CLOCK DIGITAL INPUT PIN n ON PORTx ANALOG INPUT/OUTPUT PIN n ON PORTx
Note:
1. WPx, WDx, RLx, RPxRDx I/O, SLEEP clk PUD
2514I-AVR-10/03
DATA BUS
55
Table 25 Figure 25 Table 25.
PUOE PUOV {DDxn, PORTxn, PUD} = 0b010 PUOE DDxnPORTxn PUD PUOV / / DDOV DDxn DDOE DDOV / / DDxn PVOV PVOE PORTxn PVOE PVOV PORTxn PTOE DIEOV DIEOE MCU ( ) DIEOE DIEOV / / MCU ( ) /
PUOV
DDOE DDOV PVOE
PVOV PTOE DIEOE
DIEOV DI
AIO
/

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MCU --MCUCR
/ 7 JTD R/W 0 6 - R 0 5 - R 0 4 PUD R/W 0 3 - R 0 2 - R 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* 4 - PUD: DDxn PORTxn ({DDxn, PORTxn} = 0b01) I/O P51 " " A A LCD COM0:3 SEG0:3 . Table 26. A
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 SEG3 (LCD 3) SEG2 (LCD 2) SEG1 (LCD 1) SEG0 (LCD 0) COM3 (LCD 3) COM2 (LCD 2) COM1 (LCD 1) COM0 (LCD 0)
Table 27 Table 28 A P55 Figure 25 Table 27. PA7..PA4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PA7/SEG3 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG3 PA6/SEG2 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG2 PA5/SEG1 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG1 PA4/SEG0 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG0
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Table 28. PA3..PA0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PA3/COM3 LCDEN * (LCDMUX>2) 0 LCDEN * (LCDMUX>2) 0 0 0 - LCDEN * (LCDMUX>2) 0 - COM3 PA2/COM2 LCDEN * (LCDMUX>1) 0 LCDEN * (LCDMUX>1) 0 0 0 - LCDEN * (LCDMUX>1) 0 - COM2 PA1/COM1 LCDEN * (LCDMUX>0) 0 LCDEN * (LCDMUX>0) 0 0 0 - LCDEN * (LCDMUX>0) 0 - COM1 PA0/COM0 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - COM0
B
B Table 29 Table 29. B
PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 OC2A/PCINT15 (T/C2 PWM A 15). OC1B/PCINT14 (T/C1 PWM B 14). OC1A/PCINT13 (T/C1 PWM A 13). OC0A/PCINT12 (T/C0 PWM A 12). MISO/PCINT11 (SPI MISO 11). MOSI/PCINT10 (SPI MOSI 10). SCK/PCINT9 (SPI 9). SS/PCINT8 (SPI 8).
* OC2A/PCINT15, 7 OC2 A PB7 T/C2 A (DDB7 "1") OC2 A PWM PCINT15 15 PB7 * OC1B/PCINT14, 6 OC1B B: PB6T/C1B (DDB6 "1") OC1B PWM PCINT14 14PB6
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* OC1A/PCINT13, 5 OC1A A PB5T/C1A (DDB5 "1") OC1A PWM PCINT13 13 PB5 * OC0A/PCINT12, 4 OC0A A PB4 T/C0 A (DDB4 "1") OC0A PWM PCINT12 12PB4 * MISO/PCINT11 - B, 3 MISOSPI DDB3 DDB3 PORTB3 PCINT11 11 PB3 * MOSI/PCINT10 - B, 2 MOSI SPI DDB2 DDB2 PORTB2 PCINT10 10 PB2
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* SCK/PCINT9 - B, 1 SCKSPI DDB1 DDB1 PORTB1 PCINT9 9PB1 * SS/PCINT8 - B, 0 SS: DDB0 SPI DDB0 PORTB0 PCINT8 8PB0 Table 30 Table 31 B P55 Figure 25 SPI MSTR INPUT SPI SLAVE OUTPUT MISO MOSI SPI MSTR OUTPUT SPI SLAVE INPUT Table 30. PB7..PB4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PB7/OC2A/ PCINT15 0 0 0 0 OC2A ENABLE OC2A - PCINT15 *PCIE1 1 PCINT15 INPUT - PB6/OC1B/ PCINT14 0 0 0 0 OC1BENABLE OC1B - PCINT14 * PCIE1 1 PCINT14 INPUT - PB5/OC1A/ PCINT13 0 0 0 0 OC1A ENABLE OC1A - PCINT13 * PCIE1 1 PCINT13 INPUT - PB4/OC0A/ PCINT12 0 0 0 0 OC0A ENABLE OC0A - PCINT12 *PCIE1 1 PCINT12 INPUT -
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Table 31. PB3..PB0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PB3/MISO/ PCINT11 SPE * MSTR PORTB3 * PUD SPE * MSTR 0 SPE * MSTR SPI SLAVE OUTPUT - PCINT11 * PCIE1 1 PCINT11 INPUT SPI MSTR INPUT - PB2/MOSI/ PCINT10 SPE * MSTR PORTB2 * PUD SPE * MSTR 0 SPE * MSTR SPI MSTR OUTPUT - PCINT10 * PCIE1 1 PCINT10 INPUT SPI SLAVE INPUT - PB1/SCK/ PCINT9 SPE * MSTR PORTB1 * PUD SPE * MSTR 0 SPE * MSTR SCK OUTPUT - PCINT9 * PCIE1 1 PCINT9 INPUT SCK INPUT - PB0/SS/ PCINT8 SPE * MSTR PORTB0 * PUD SPE * MSTR 0 0 0 - PCINT8 *PCIE1 1 PCINT8 INPUT SPI SS -
C
C LCD SEG5:12 Table 32. C
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 SEG5 (LCD 5) SEG6 (LCD 6) SEG7 (LCD 7) SEG8 (LCD 8) SEG9 (LCD 9) SEG10 (LCD 10) SEG11 (LCD 11) SEG12 (LCD 12)
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Table 33 Table 34 C P55 Figure 25 . Table 33. PC7..PC4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PC7/SEG5 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG5 PC6/SEG6 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG6 PC5/SEG7 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG7 PC4/SEG8 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG8
Table 34. PC3..PC0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PC3/SEG9 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG9 PC2/SEG10 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG10 PC1/SEG11 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG11 PC0/SEG12 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG12
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D D Table 35. Table 35. D
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 SEG15 (LCD 15) SEG16 (LCD 16) SEG17 (LCD 17) SEG18 (LCD 18) SEG19 (LCD 19) SEG20 (LCD 20) INT0/SEG21 ( 0 LCD 21) ICP1/SEG22 (T/C1 LCD 22)
* SEG15 - SEG20 - D, 7:2 SEG15-SEG20, LCD 15-20 * INT0/SEG21 - D, 1 INT0 0 PD1 MCU SEG21 LCD 21 * ICP1/SEG22 - D, 0 ICP1 - 1PD0 T/C1 SEG22 LCD 22
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Table 36 Table 37 D P55 Figure 25 Table 36. PD7..PD4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PD7/SEG15 LCDEN * (LCDPM>1) 0 LCDEN * (LCDPM>1) 0 0 0 - LCDEN * (LCDPM>1) 0 - SEG15 PD6/SEG16 LCDEN * (LCDPM>1) 0 LCDEN * (LCDPM>1) 0 0 0 - LCDEN * (LCDPM>1) 0 - SEG16 PD5/SEG17 LCDEN * (LCDPM>2) 0 LCDEN * (LCDPM>2) 0 0 0 - LCDEN * (LCDPM>2) 0 - SEG17 PD4/SEG18 LCDEN * (LCDPM>2) 0 LCDEN * (LCDPM>2) 0 0 0 - LCDEN * (LCDPM>2) 0 - SEG18
Table 37. PD3..PD0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PD3/SEG19 LCDEN * (LCDPM>3) 0 LCDEN * (LCDPM>3) 0 0 0 - LCDEN * (LCDPM>3) 0 - - PD2/SEG20 LCDEN * (LCDPM>3) 0 LCDEN * (LCDPM>3) 0 0 0 - LCDEN * (LCDPM>3) 0 - - PD1/INT0/SEG21 LCDEN * (LCDPM>4) 0 LCDEN * (LCDPM>4) 0 0 0 - LCDEN + (INT0 ENABLE) LCDEN * (INT0 ENABLE) INT0 INPUT PD0/ICP1/SEG22 LCDEN * (LCDPM>4) 0 LCDEN * (LCDPM>4) 0 0 0 - LCDEN * (LCDPM>4) 0 ICP1 INPUT
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E E Table 38. Table 38. E
PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PCINT7 ( 7) CLKO ( ) DO/PCINT6 (USI 6) DI/SDA/PCINT5 (USI TWI 5) USCK/SCL/PCINT4 (USART / TWI 4) AIN1/PCINT3 ( 3) XCK/AIN0/ PCINT2 (USART 2) TXD/PCINT1 (USART 1) RXD/PCINT0 (USART 0)
* PCINT7 - E, 7 PCINT7 7PE7 CLKO PE7 CKOUT PORTE7 DDE7 PE7 * DO/PCINT6 - E, 6 DO USI PCINT6 6PE6 * DI/SDA/PCINT5 - E, 5 DI USI SDA PCINT5 5 PE5 * USCK/SCL/PCINT4 - E, 4 USCK USI SCL PCINT4 4 PE4 * AIN1/PCINT3 - E, 3 AIN1 - PCINT3 3PE3 * XCK/AIN0/PCINT2 - E, 2 XCK USART DDE2 (DDE2 "0") (DDE2 "1") USART XCK AIN0 - 65
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PCINT2 2PE2 * TXD/PCINT1 - E, 1 TXD0 UART0 PCINT1 1PE1 * RXD/PCINT0 - E, 0 RXD USART ( USART ) USART DDE0 PORTE0 PCINT0 0PE0 Table 39 Table 40 E P55 Figure 25 Table 39. PE7..PE4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: PE7/PCINT7 0 0 CKOUT 1 CKOUT(1) clkI/O - PCINT7 * PCIE0 1 PCINT7 INPUT -
(1)
PE6/DO/ PCINT6 0 0 0 0 USI_THREEWIRE DO - PCINT6 * PCIE0 1 PCINT6 INPUT -
PE5/DI/SDA/ PCINT5 USI_TWO-WIRE 0 USI_TWO-WIRE (SDA + PORTE5) * DDE5 USI_TWO-WIRE * DDE5 0 - (PCINT5 * PCIE0) + USISIE 1 DI/SDA INPUT PCINT5 INPUT -
PE4/USCK/SCL/ PCINT4 0 0 USI_TWO-WIRE (USI_SCL_HOLD + PORTE4) + DDE4 USI_TWO-WIRE * DDE4 0 USITC (PCINT4 * PCIE0) + USISIE 1 USCKL/SCL INPUT PCINT4 INPUT -
1. CKOUT CKOUT "1"
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Table 40. PE3..PE0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE PE3/AIN1/ PCINT3 0 0 0 0 0 0 - (PCINT3 * PCIE0) + AIN1D(1) PCINT3 * PCIE0 PCINT3 INPUT AIN1 INPUT PE2/XCK/AIN0/ PCINT2 0 0 0 0 XCK XCK - (PCINT2 * PCIE0) + AIN0D(1) PCINT2 * PCIE0 XCK/PCINT2 INPUT AIN0 INPUT PE1/TXD/ PCINT1 TXEN 0 TXEN 1 TXEN TXD - PCINT1 * PCIE0 1 PCINT1 INPUT - PE0/RXD/PCINT0 RXEN PORTE0 * PUD RXEN 0 0 0 - PCINT0 * PCIE0
DIEOV DI AIO Note:
1 RXD/PCINT0 INPUT -
1. AIN0D AIN1D P183 " 1 - DIDR1"
F
Table 41 F ADC F AD JTAG PF7(TDI) PF5(TMS) PF4(TCK) Table 41. F
PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ADC7/TDI (ADC 7 JTAG ) ADC6/TDO (ADC 6 JTAG ) ADC5/TMS (ADC 5 JTAG ) ADC4/TCK (ADC 4 JTAG ) ADC3 (ADC 3) ADC2 (ADC 2) ADC1 (ADC 1) ADC0 (ADC 0)
* TDI, ADC7 - F, 7 ADC7 7 TDIJTAG ( ) JTAG I/O * TDO, ADC6 - F, 6 ADC6 6
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2514I-AVR-10/03
TDOJTAG JTAG I/O TAP TDO * TMS, ADC5 - F, 5 ADC5 5 TMS JTAG TAP JTAG I/O * TCK, ADC4 - F, 4 ADC4 4 TCK JTAG JTAG TCK JTAG I/O * ADC3 - ADC0 - F, 3:0 3..0 Table 42. PF7..PF4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PF7/ADC7/TDI JTAGEN 1 JTAGEN 0 0 0 - JTAGEN 0 - TDI ADC7 INPUT PF6/ADC6/TDO JTAGEN 1 JTAGEN SHIFT_IR + SHIFT_DR JTAGEN TDO - JTAGEN 0 - ADC6 INPUT PF5/ADC5/TMS JTAGEN 1 JTAGEN 0 0 0 - JTAGEN 0 - TMS ADC5 INPUT PF4/ADC4/TCK JTAGEN 1 JTAGEN 0 0 0 - JTAGEN 0 - TCK ADC4 INPUT
68
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Table 43. PF3..PF0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PF3/ADC3 0 0 0 0 0 0 - 0 0 - ADC3 INPUT PF2/ADC2 0 0 0 0 0 0 - 0 0 - ADC2 INPUT PF1/ADC1 0 0 0 0 0 0 - 0 0 - ADC1 INPUT PF0/ADC0 0 0 0 0 0 0 - 0 0 - ADC0 INPUT
G
Table 44. G
PG4 PG3 PG2 PG1 PG0 T0/SEG23 (T/C0 LCD 23) T1/SEG24 (T/C1 LCD 24) SEG4 (LCD 4) SEG13 (LCD 13) SEG14 (LCD 14)
* T0/SEG23 - G, 4 T0 T/C0 SEG23 LCD 23 * T1/SEG24 - G, 3 T1 T/C1 SEG24 LCD 24 * SEG4 - G, 2 SEG4 LCD 4 * SEG13 - G, 1 SEG13 13 * SEG14 - G, 0 SEG14 LCD 14 69
2514I-AVR-10/03
Table 44 Table 45 G P55 Figure 25 . Table 45. PG4
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO - - - PG4/T0/SEG23 LCDEN * (LCDPM>5) 0 LCDEN * (LCDPM>5) 1 0 0 - LCDEN * (LCDPM>5) 0 T0 INPUT SEG23
Table 46. PG3:0
PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO PG3/T1/SEG24 LCDEN * (LCDPM>6) 0 LCDEN * (LCDPM>6) 0 0 0 - LCDEN * (LCDPM>6) 0 T1 INPUT SEG24 PG2/SEG4 LCDEN 0 LCDEN 0 0 0 - LCDEN 0 - SEG4 PG1/SEG13 LCDEN * (LCDPM>0) 0 LCDEN * (LCDPM>0) 0 0 0 - LCDEN * (LCDPM>0) 0 - SEG13 PG0/SEG14 LCDEN * (LCDPM>0) 0 LCDEN * (LCDPM>0) 0 0 0 - LCDEN * (LCDPM>0) 0 - SEG14
70
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
I/O
A --PORTA
/ 7
PORTA7
6
PORTA6
5
PORTA5
4
PORTA4
3
PORTA3
2
PORTA2
1
PORTA1
0
PORTA0
PORTA
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
A --DDRA
/
7 DDA7 R/W 0
6 DDA6 R/W 0
5 DDA5 R/W 0
4 DDA4 R/W 0
3 DDA3 R/W 0
2 DDA2 R/W 0
1 DDA1 R/W 0
0 DDA0 R/W 0 DDRA
A --PINA
/
7 PINA7 R/W N/A
6 PINA6 R/W N/A
5 PINA5 R/W N/A
4 PINA4 R/W N/A
3 PINA3 R/W N/A
2 PINA2 R/W N/A
1 PINA1 R/W N/A
0 PINA0 R/W N/A PINA
B --PORTB
/
7
PORTB7
6
PORTB6
5
PORTB5
4
PORTB4
3
PORTB3
2
PORTB2
1
PORTB1
0
PORTB0 PORTB
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
B --DDRB
/
7 DDB7 R/W 0
6 DDB6 R/W 0
5 DDB5 R/W 0
4 DDB4 R/W 0
3 DDB3 R/W 0
2 DDB2 R/W 0
1 DDB1 R/W 0
0 DDB0 R/W 0 DDRB
B --PINB
/
7 PINB7 R/W N/A
6 PINB6 R/W N/A
5 PINB5 R/W N/A
4 PINB4 R/W N/A
3 PINB3 R/W N/A
2 PINB2 R/W N/A
1 PINB1 R/W N/A
0 PINB0 R/W N/A PINB
C --PORTC
/
7
PORTC7
6
PORTC6
5
PORTC5
4
PORTC4
3
PORTC3
2
PORTC2
1
PORTC1
0
PORTC0 PORTC
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
C --DDRC
/
7 DDC7 R/W 0
6 DDC6 R/W 0
5 DDC5 R/W 0
4 DDC4 R/W 0
3 DDC3 R/W 0
2 DDC2 R/W 0
1 DDC1 R/W 0
0 DDC0 R/W 0 DDRC
71
2514I-AVR-10/03
C --PINC
/
7 PINC7 R/W N/A
6 PINC6 R/W N/A
5 PINC5 R/W N/A
4 PINC4 R/W N/A
3 PINC3 R/W N/A
2 PINC2 R/W N/A
1 PINC1 R/W N/A
0 PINC0 R/W N/A PINC
D --PORTD
/
7
PORTD7
6
PORTD6
5
PORTD5
4
PORTD4
3
PORTD3
2
PORTD2
1
PORTD1
0
PORTD0 PORTD
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
D --DDRD
/
7 DDD7 R/W 0
6 DDD6 R/W 0
5 DDD5 R/W 0
4 DDD4 R/W 0
3 DDD3 R/W 0
2 DDD2 R/W 0
1 DDD1 R/W 0
0 DDD0 R/W 0 DDRD
D --PIND
/
7 PIND7 R/W N/A
6 PIND6 R/W N/A
5 PIND5 R/W N/A
4 PIND4 R/W N/A
3 PIND3 R/W N/A
2 PIND2 R/W N/A
1 PIND1 R/W N/A
0 PIND0 R/W N/A PIND
E --PORTE
/
7
PORTE7
6
PORTE6
5
PORTE5
4
PORTE4
3
PORTE3
2
PORTE2
1
PORTE1
0
PORTE0 PORTE
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
E --DDRE
/
7 DDE7 R/W 0
6 DDE6 R/W 0
5 DDE5 R/W 0
4 DDE4 R/W 0
3 DDE3 R/W 0
2 DDE2 R/W 0
1 DDE1 R/W 0
0 DDE0 R/W 0 DDRE
E --PINE
/
7 PINE7 R/W N/A
6 PINE6 R/W N/A
5 PINE5 R/W N/A
4 PINE4 R/W N/A
3 PINE3 R/W N/A
2 PINE2 R/W N/A
1 PINE1 R/W N/A
0 PINE0 R/W N/A PINE
F --PORTF
/
7
PORTF7
6
PORTF6
5
PORTF5
4
PORTF4
3
PORTF3
2
PORTF2
1
PORTF1
0
PORTF0 PORTF
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
F --DDRF
/
7 DDF7 R/W 0
6 DDF6 R/W 0
5 DDF5 R/W 0
4 DDF4 R/W 0
3 DDF3 R/W 0
2 DDF2 R/W 0
1 DDF1 R/W 0
0 DDF0 R/W 0 DDRF
72
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
F --PINF
/ 7 PINF7 R/W N/A 6 PINF6 R/W N/A 5 PINF5 R/W N/A 4 PINF4 R/W N/A 3 PINF3 R/W N/A 2 PINF2 R/W N/A 1 PINF1 R/W N/A 0 PINF0 R/W N/A PINF
G --PORTG
/
7 - R 0
6 - R 0
5 - R 0
4
PORTG4
3
PORTG3
2
PORTG2
1
PORTG1
0
PORTG0 PORTG
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
G --DDRG
/
7 - R 0
6 - R 0
5 - R 0
4 DDG4 R/W 0
3 DDG3 R/W 0
2 DDG2 R/W 0
1 DDG1 R/W 0
0 DDG0 R/W 0 DDRG
G --PING
/
7 - R 0
6 - R 0
5 - R 0
4 PING4 R/W N/A
3 PING3 R/W N/A
2 PING2 R/W N/A
1 PING1 R/W N/A
0 PING0 R/W N/A PING
73
2514I-AVR-10/03
INT0 PCINT15..0 INT0 PCINT15..0 PCINT15..8 PCI1 PCINT7..0 PCI0 PCMSK1 PCMSK0 PCINT15..0 INT0 A - EICRA INT0 INT0 I/O ( P23 " " )INT0 ( ) I/O MCU MCU MCU SUT CKSEL P23" "
A--EICRA
A
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 EICRA
* 1, 0 - ISC01, ISC00: 0 1 0 0 INT0 SREG I Table 47 MCU INT0 Table 47. 0
ISC01 0 0 1 1 ISC00 0 1 0 1 INT0 INT0 INT0 INT0
74
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
--EIMSK
/ 7 PCIE1 R/W 0 6 PCIE0 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 INT0 R/W 0 EIMSK
* 7 - PCIE1: 1 PCIE1 "1" SREG I 1 PCINT15..8 PCI1 PCINT15..8 PCMSK1 * 6 - PCIE0: 0 PCIE0 "1" SREG I 0 PCINT7..0 PCI0 PCINT7..0 PCMSK0 * 0 - INT0: 0 INT0 "1" SREG I - EICRA INT0 INT0 INT0 --EIFR
/ 7 PCIF1 R/W 0 6 PCIF0 R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 INTF0 R/W 0 EIFR
* 7 - PCIF1: 1 PCINT15..8 PCIF1 SREGIEIMSKPCIE1"1" MCU "1" * 6 - PCIF0: 0 PCINT7..0 PCIF0 SREGIEIMSKPCIE0"1" MCU "1" * 0 - INTF0: 0 INT0 INTF0 SREG I EIMSK INT0 "1" MCU "1" INTF0 INTF0 1-- PCMSK1
/ 7
PCINT15
6
PCINT14
5
PCINT13
4
PCINT12
3
PCINT11
2
PCINT10
1
PCINT9
0
PCINT8 PCMSK1
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
75
2514I-AVR-10/03
* 7..0 - PCINT15..8: 15..8 PCINT15..8 I/O PCINT15..8 EIMSK PCIE1 PCINT15..8 0-- PCMSK0
/ 7 PCINT7 R/W 0 6 PCINT6 R/W 0 5 PCINT5 R/W 0 4 PCINT4 R/W 0 3 PCINT3 R/W 0 2 PCINT2 R/W 0 1 PCINT1 R/W 0 0 PCINT0 R/W 0 PCMSK0
* 7..0 - PCINT7..0: 7..0 PCINT7..0 I/O PCINT7..0 EIMSK PCIE0 PCINT7..0
76
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
PWM 8 / 0
T/C0 8 / * * ( ) * PWM * * * 10 * (TOV0 OCF0A) Figure 26 8 / P2 "ATmega169 " CPU I/O I/O P86 "8 / " Figure 26. 8 T/C
TCCRn
count clear direction Control Logic Clock Select Edge Detector BOTTOM TOP
TOVn (Int.Req.) clk Tn
Tn
DATA BUS
( From Prescaler ) Timer/Counter TCNTn
=0
= 0xFF
OCn (Int.Req.)
=
Waveform Generation
OCn
OCRn
T/C(TCNT2) (OCR2) 8 ( Int.Req. ) TIFR0 TIMSK0 TIFR0 TIMSK0 T/C T0 ( )T/C T/C clkT0 OCR0A T/C PWM OC0A P79"" OCF0A
"n" T/C 0 "x" A TCNT0 T/C0
77
2514I-AVR-10/03
Table 48 Table 48. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR0A
T/C
T/C T/C TCCR0A CS02:0 P90 "T/C0 T/C1 " 8T/CFigure 27 Figure 27.
DATA BUS
TOVn (Int.Req.)
Clock Select count TCNTn clear direction ( From Prescaler ) bottom top Control Logic clkTn Edge Detector Tn
( ) count direction clear clkTn top bottom TCNT0 1 1 TCNT0 ( ) T/C clkT0 TCNT0 TCNT0 (0)
78
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
clkT0 clkT0 CS02:0 (CS02:0 = 0) clkT0 CPU TCNT0 CPU ( ) T/C (TCCR0A) WGM01 WGM00 OC0A P82 " " T/CTOV0WGM01:0 TOV0CPU
8TCNT0OCR0A TCNT0OCR0A OCF0A OCIE0A = 1 SREG I CPU OCF0A "1" WGM21:0 COM01:0 max bottom (P82 " " ) Figure 28 Figure 28.
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top bottom FOCn
Waveform Generator
OCnx
WGMn1:0
COMnx1:0
79
2514I-AVR-10/03
PWM OCR0A OCR0 top bottom PWM OCR0A CPU OCR0A CPU OCR0A PWM FOC0A "1" OCF0A / OC0A (COM0A1:0 OC0A "0""1" ) CPU TCNT0 OCR0A TCNT0 TCNT0 TCNT0 T/C TCNT0 OCR0A TCNT0 BOTTOM OC0A OC0A FOC0A OC0A COM0A1:0 COM0A1:0
TCNT0
80
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
COM0A1:0 COM0A1:0 (OC0A) COM0A1:0 OC0A Figure 29 COM0A1:0 I/O I/O I/O COM0A1:0 I/O (DDR PORT) OC0A OC0A OC0A OC0A Figure 29.
COMnx1 COMnx0 FOCn
Waveform Generator
D
Q
1 OCn Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM0A1:0 I/O OC0ADDR OC0A DDR_OC0A OC0A COM0A1:0 P86 "8 / " COM0A1:0 CTC PWM COM0A1:0 = 0 OC0A PWM P87 Table 50 PWM P87 Table 51 PWM P87 Table 52 COM0A1:0 PWM FOC0A
81
2514I-AVR-10/03
- T/C - (WGM01:0) (COM0A1:0) COM0A1:0 PWM PWM COM0A1:0 (P81" " ) P85"T/C " Figure 33 Figure 34 Figure 35 Figure 36
(WGM01:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV0 TOV0 9 TOV0 CPU
CTC( )
CTC (WGM01:0 = 2) OCR0A TCNT0 OCR0A OCR0A TOP CTC Figure 30 TCNT0 TCNT0 OCR0A TCNT0 Figure 30. CTC
OCnx Interrupt Flag Set
TCNTn
OCn (Toggle) Period
1 2 3 4
(COMnx1:0 = 1)
OCF0A TOP TOP CTC TOP BOTTOM OCR0A TCNT0 0xFF 0x00 OCF0A CTC OC0A COM0A1:0 = 1 OC0A fOC0 = fclk_I/O/2 (OCR0 = 0x00) f clk_I/O f OCnx = --------------------------------------------------2 N ( 1 + OCRnx ) N (1 8 64 1024)
82
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
TOV0 MAX 0x00 PWM PWM (WGM01:0 = 3) PWM PWM PWM BOTTOMMAX BOTTOM OC0ATCNT0OCR0A BOTTOM OC0A PWM PWM PWM DAC ( ) PWM MAX Figure 31 TCNT0 PWM PWM TCNT0 OCR0A TCNT0 Figure 31. PWM
OCRnx Interrupt Flag Set
OCRnx Update and TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
MAX T/C TOV0 PWM OC0A PWM COM0A1:0 2 PWM 3 PWM ( P87 Table 51 ) OC0A PWM OC0A OCR0A TCNT0 ( ) ( MAX BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = -----------------N 256 N (1 8 64 256 1024) OCR0A PWM OCR0A BOTTOM MAX+1OCR0AMAX COM0A1:0 OC0A (COM0A1:0 = 1) 50% OCR0A0foc2 = fclk_I/O/2 CTC OC0A PWM 83
2514I-AVR-10/03
PWM
PWM (WGM01:0 = 1) PWM BOTTOM MAX MAX BOTTOM MAX TCNT0 OCR0A OC0A BOTTOM TCNT0 OCR0A OC0A PWM PWM 8 MAX TCNT0 MAX Figure 32 TCNT0 PWM PWM TCNT0 OCR0A TCNT0 Figure 32. PWM
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCn OCn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV0 PWM OC0A PWM COM0A1:0 2 PWM COM0A1:0 3 PWM ( P87 Table 52 ) OC0A OCR0A TCNT0 OC0A PWM PWM f clk_I/O f OCnxPCPWM = -----------------N 510 N (1 8 64 256 1024) OCR0A PWM PWM OCR0A BOTTOM OCR0A MAX PWM Figure 32 2 OCn BOTTOM
84
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
* Figure 32 OCR0A MAX OCR0A MAX OCn BOTTOM T/C MAX OCn OCn OCR0A BOTTOM OCn OCn
*
T/C
T/C clkT2 Figure 33 T/C PWM MAX Figure 33. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 34 Figure 34. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 35 ( CTC )OCF0A Figure 35. T/C OCF0A fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
85
2514I-AVR-10/03
Figure 36 CTC OCF0A TCNT0 Figure 36. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
8 /
T/C A--TCCR0A
/ 7
FOC0A
6
WGM00
5
COM0A1
4
COM0A0
3
WGM01
2
CS02
1
CS01
0
CS00 TCCR0
W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* 7 - FOC0A: A FOC0A WGM00 PWM PWM TCCR0 1 OC0A COM0A1:0 FOC0A COM0A1:0 FOC0A OCR0ATOPCTC FOC0A 0 * 6, 3 - WGM01:0: TOP T/C (CTC) PWM Table 49 P82 " "
86
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Table 49.
WGM01 (CTC0) 0 0 1 1 WGM00 (PWM0) 0 1 0 1 OCR0A TOP TOP TOV0 MAX BOTTOM MAX MAX
0 1 2 3 Note:
T/C PWM CTC PWM
TOP 0xFF 0xFF OCR0A 0xFF
1. CTC0 PWM0 WGM01:0
* 5:4 - COM0A1:0: OC0A COM0A1:0 OC0A 1 OC0A COM0A1:0 WGM01:0 Table 50 WGM01:0 CTC COM0A1:0 . Table 50. PWM
COM0A1 0 0 1 1 COM0A0 0 1 0 1 OC0A OC0A OC0A OC0A
Table 51 WGM01:0 PWM COM0A1:0 . Table 51. PWM (1)
COM0A1 0 0 1 1 Note: COM0A0 0 1 0 1 OC0A OC0A TOP OC0A OC0A TOP OC0A
1. OCR0A TOP COM0A1 TOP OC0A P83" PWM "
Table 52 WGM01:0 PWM COM0A1:0 Table 52. PWM (1)
COM0A1 0 COM0A0 0 OC0A
87
2514I-AVR-10/03
Table 52. PWM (1)
COM0A1 0 1 1 Note: COM0A0 1 0 1 OC0A OC0A OC0A OC0A
1. OCR0A TOP COM0A1 TOP OC0A P84 " PWM "
* 2:0 - CS02:0: T/C Table 53.
CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 T/C clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T0 T0
T/C0 T0 T/C --TCNT0
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 TCNT0 R/W 0
TCNT0[7:0]
T/C 8 TCNT0 TCNT0 TCNT0 OCR0A
88
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
A--OCR0A
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR0 R/W 0
OCR0A[7:0]
A 8 TCNT0 OC0A T/C0 --TIMSK0
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 OCIE0A R/W 0 0 TOIE0 R/W 0 TIMSK0
* 1 - OCIE0A: T/C0 A OCIE0A I "1" T/C0 A T/C0 TIFR0 OCF0A * 0 - TOIE0: T/C0 TOIE0 I "1" T/C0 T/C0 TIFR0 TOV0 T/C0 --TIFR0
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 OCF0A R/W 0 0 TOV0 R/W 0 TIFR0
* 1 - OCF0A: 0 A T/C0 OCR0A( 0) OCR0A 1 SREG I OCIE0A(T/C0 ) OCF0A * 0 - TOV0: T/C0 T/C0 TOV0 TOV0 1 SREG I TOIE0(T/C0 ) TOV0 PWM T/C0 0x00 TOV0
89
2514I-AVR-10/03
T/C0 T/C1
T/C1 T/C0 T/C1 T/C0 CSn2:0 = 1 T/C T/C fCLK_I/O 4 fCLK_I/O/8 fCLK_I/O/64 fCLK_I/O/256 fCLK_I/O/1024 T/C T/C1 T/C0 T/C (6 > CSn2:0 > 1) 1 N+1 N (8 64 256 1024) T/C T/C T/C
T1/T0 T/C clkT1/clkT0 T1/T0 ( ) Figure 37 T1/T0 clkI/O CSn2:0 = 7 clkT1 CSn2:0 = 6 clkT0 Figure 37. T1/T0
Tn_sync (To Clock Select Logic)
Tn
D LE
Q
D
Q
D
Q
clk I/O
Synchronization Edge Detector
T1/T0 2.5 3.5 T1/T0 T/C 50% (fExtClk < fclk_I/O/2) (Nyquist ) ( ) fclk_I/O/2.5
90
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Figure 38. T/C0 T/C1
clk I/O
Clear
PSR10
T0
Synchronization
T1
Synchronization
clkT1
clkT0
Note:
1. (T1/T0) Figure 37
T/C --GTCCR
/
7 TSM R/W 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 PSR2 R/W 0
0 PSR10 R/W 0 GTCCR
* 7 - TSM: T/C TSMT/C TSM PSR2 PSR10 / T/C / T/C TSM PSR2 PSR10 / * 0 - PSR10: T/C1 T/C0 T/C1 T/C0 TSM T/C1 T/C0
91
2514I-AVR-10/03
16 / 1
16T/C() * 16 ( 16 PWM) * 2 * * * * ( ) * PWM * PWM * * * 4 (TOV1OCF1A OCF1B ICF1) "n" T/C "x" TCNT1 T/C1 16T/C Figure 39 I/OP2 "ATmega169 " CPUI/O I/OI/O I/O P112 "16 / " Figure 39. 16 T/C (1)
Count Clear Direction Control Logic TOVn (Int.Req.) clkTn Clock Select Edge Detector TOP BOTTOM ( From Prescaler ) Timer/Counter TCNTn Tn
=
=0
OCnA (Int.Req.)
=
OCRnA Fixed TOP Values
Waveform Generation
OCnA
DATA BUS
OCnB (Int.Req.) Waveform Generation OCnB
=
OCRnB ICFn (Int.Req.) Edge Detector
( From Analog Comparator Ouput )
ICRn
Noise Canceler ICPn
TCCRnA
TCCRnB
Note:
1. P2 Figure 1 P58Table 28 P62 Table 34 T/C1
92
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
/ TCNT1 OCR1A/B ICR1 16 16 P94 " 16 " T/C TCCR1A/B 8 CPU ( Int.Req.) TIFR1 TIMSK1 TIFR1 TIMSK1 T/CT1 T/C( ) T/C clkT1 OCR1A/B T/C PWMOC1A/B P99 "" OCF1A/B ICP1 ( P181 " " ) ( ) T/C ( ) TOP T/C OCR1A ICR1 PWM OCR1A TOP OCR1A PWM OCR1A TOP TOP ICR1 OCR1A PWM Table 54.
BOTTOM MAX TOP 0x0000 BOTTOM 0xFFFF ( 65535) MAX TOP TOP 0x00FF 0x01FF 0x03FF OCR1A ICR1
16T/C16AVRT/C * * * * * * * * 16 T/C I/O 16 T/C PWM10 WGM10 PWM11 WGM11 CTC1 WGM12 TCCR1C FOC1A FOC1B TCCR1B WGM13
16 T/C
16 T/C
93
2514I-AVR-10/03
16
TCNT1 OCR1A/B ICR1 AVR CPU 8 16 16 1688 16 16 16 CPU 16 8 8 16 16 CPU 16 16 OCR1A/B 16 16 16 OCR1A/B ICR1 "C" 16 (1)
... ; TCNT1 0x01FF ldi r17,0x01 ldi r16,0xFF out TCNT1H,r17 out TCNT1L,r16 ; TCNT1 r17:r16 in in ... r16,TCNT1L r17,TCNT1H
C (1)
unsigned int i; ... /* TCNT1 0x01FF */ TCNT1 = 0x1FF; /* TCNT1 i */ i = TCNT1; ...
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
TCNT1 r17:r16 16 16 16 16 16
94
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
TCNT1 OCR1A/B ICR1 (1)
TIM16_ReadTCNT1: ; in cli ; TCNT1 r17:r16 in in r16,TCNT1L r17,TCNT1H r18,SREG ; *
; out SREG,r18 ret
C (1)
unsigned int TIM16_ReadTCNT1( void ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ i = TCNT1; /* */ SREG = sreg; return i; }
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
TCNT1 r17:r16
95
2514I-AVR-10/03
TCNT1 OCR1A/B ICR1 (1)
TIM16_WriteTCNT1: ; in cli ; TCNT1 r17:r16 out TCNT1H,r17 out TCNT1L,r16 ; out SREG,r18 ret r18,SREG ; *
C (1)
void TIM16_WriteTCNT1( unsigned int i ) { unsigned char sreg; unsigned int i; /* */ sreg = SREG; /* */ _CLI(); /* TCNT1 i */ TCNT1 = i; /* */ SREG = sreg; }
Note:
1. I/O I/O "LDS" "STS""SBRS""SBRC""SBR" "CBR" I/O "IN" "OUT" "SBIS""SBIC" "CBI" "SBI"
r17:r16 TCNT1 16
96
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
T/C
T/C T/C B(TCCR1B) (CS12:0) P90 "T/C0 T/C1 " 16 T/C 16 Figure 40 Figure 40.
DATA BUS
(8-bit) TOVn (Int.Req.) TEMP (8-bit) Clock Select Count TCNTnH (8-bit) TCNTnL (8-bit) Clear Direction Control Logic clkTn Edge Detector Tn
TCNTn (16-bit Counter)
( From Prescaler ) TOP BOTTOM
( ) Count Direction Clear clkT1 TOP BOTTOM TCNT1 1 1 TCNT1 / TCNT1 TCNT1 (0)
16 8 I/O TCNT1H 8 TCNT1L 8 CPU TCNT1H CPU TCNT1H (TEMP) TCNT1L TCNT1HTCNT1L TCNT1H CPU 8 16 TCNT1 clkT1 1 1 clkT1 CS12:0 CS12:0= 0 CPU TCNT1 clkT1 CPU TCCR1A TCCR1B WGM13:0 ( ) OC1x P102 " " WGM13:0 TOV1 TOV1 CPU
T/C ICP1 Figure 41 "n" /
97
2514I-AVR-10/03
Figure 41. I
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit) WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
ACO* Analog Comparator ICPn
ACIC*
ICNC
ICES
Noise Canceler
Edge Detector
ICFn (Int.Req.)
ICP1 ( ) ACO 16 TCNT1 ICR1 ICF1 ICIE1 = 1 ICF1 I/O "1" ICR1 ICR1L ICR1H TEMP CPU ICR1H TEMP ICR1 ICR1 TOP ICR1 WGM13:0 ICR1 ICR1H I/O ICR1L P94 " 16 " 16 ICP1T/C1 ACSR ACIC ICP1 ACO T1 (P90 Figure 37 ), 4 ICR1 TOP T/C ICP1 4 4 TCCR1B ICNC1 ICR1 4
98
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
ICR1 ICR1 ICR1 TOP ICR1 ICF1 ( I/O "1") ICF1
16 TCNT1 OCR1x OCF1x OCIE1x = 1 OCF1x OCF1x I/O "1" WGM13:0 COM1x1:0 TOP BOTTOM (P102 " " ) A T/C TOP ( ) TOP Figure 42 "n" (n = 1 T/C1) "x" (A/B) Figure 42.
DATA BUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.) TOP BOTTOM
Waveform Generator
OCnx
WGMn3:0
COMnx1:0
T/C 12 PWM OCR1x (CTC) OCR1x TOP BOTTOM PWM OCR1x CPU OCR1x CPU OCR1x OCR1x( ) (T/C TCNT1 ICR1 99
2514I-AVR-10/03
) OCR1x TEMP 16 OCR1x TEMP OCR1xH CPU I/O TEMP OCR1xL TEMP OCR1x OCR1x P94 " 16 " 16 PWM FOC1x "1" OCF1x / OC1x (COMx1:0 OC1x ) CPUTCNT1 OCR1x TCNT1 TCNT1 TCNT1 T/C TCNT1OCR1x PWM TOP TCNT1 TOP 0xFFFF TCNT1BOTTOM OC1x OC1x FOC1x OC1x COM1x1:0 COM1x1:0
TCNT1
100
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
COM1x1:0 COM1x1:0 OC1x COM1x1:0 OC1x Figure 43 COM1x1:0 I/O I/O I/O COM1x1:0 I/O (DDR PORT) OC1x OC1x OC1x COM1x "0" Figure 43.
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM1x1:0 OC1x I/O OC1x (DDR) OC1x DDR_OC1x Table 55 Table 56 Table 57 OC1x COM1x1:0 P112 "16/" COM1x1:0
101
2514I-AVR-10/03
COM1x1:0 CTC PWM COM1x1:0 = 0 OC1x PWM P112 Table 55 PWM P112 Table 56 PWM P113 Table 57 COM1x1:0 PWM FOC1x
- T/C - (WGM13:0) (COM1x1:0) COM1x1:0 PWM PWM COM1x1:0 ( P101 " " ) P110 " / "
(WGM13:0 = 0) (TOP = 0xFFFF) 0x0000 TCNT1T/CTOV1 TOV117 TOV1 CPU
102
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
CTC( ) CTC (WGM13:0 = 4 12) OCR1A ICR1 TCNT1 OCR1A(WGM13:0 = 4) ICR1 (WGM13:0 = 12) OCR1A ICR1 TOP CTCFigure 44 TCNT1TCNT1OCR1A ICR1 TCNT1 Figure 44. CTC
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnA (Toggle) Period
1 2 3 4
(COMnA1:0 = 1)
OCF1A ICF1 TOP TOP CTC TOP BOTTOM OCR1A ICR1 TCNT1 0xFFFF 0x0000 OCR1A ICR1 CTC OC0A COM1A1:0 = 1 OC1A (DDR_OC1A = 1) fOC2 = fclk_I/O/2 (OCR1A = 0x0000) f clk_I/O f OCnA = ---------------------------------------------------2 N ( 1 + OCRnA ) N (1 8 64 256 1024) TOV1 MAX 0x0000
103
2514I-AVR-10/03
PWM
PWM (WGM13:0 = 5 6 7 14 15) PWM PWM PWM BOTTOM MAX BOTTOM OC1x TCNT1 OCR1x TOP OCR1x PWM PWM PWM DAC ( ) PWM PWM 89 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R FPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 5 6 7)ICR1 (WGM13:0 = 14) OCR1A (WGM13:0 = 15) Figure 45 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 45. PWM
OCRnx / TOP Update and TOVn Interrupt Flag Set and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
TOP T/C TOV1 TOP OCR1A ICR1 OC1A ICF1 TOV1 TOP TOPTOP TCNT1OCR1x TOP OCR1x "0" TOP ICR1 OCR1A ICR1 ICR1 ICR1 TCNT1 0xFFFF 0x0000 OCR1A OCR1A OCR1A TCNT1 TOP OCR1A TCNT1 TOV1
104
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P112 Table ) OC1x DDR_OC1x PWM OC1x OCR1x TCNT1 ( ) ( TOP BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = ----------------------------------N ( 1 + TOP ) N (1 8 64 256 1024) OCR1x PWM OCR1x BOTTOM(0x0000) TOP+1OCR1xTOP COM1x1:0 OC1A (COM1A1:0 = 1) 50% OCR1A TOP (WGM13:0 = 15) OCR1A 0(0x0000) foc2 = fclk_I/O/2 CTC OC1A PWM
105
2514I-AVR-10/03
PWM
PWM (WGM13:0 = 1 2 3 11) 10 PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1x BOTTOM TCNT1 OCR1x OC1x PWM PWM 8 9 10 ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PCPWM = ----------------------------------log ( 2 ) PWM 0x00FF 0x01FF 0x03FF (WGM13:0 = 12 3) ICR1 (WGM13:0 = 10) OCR1A (WGM13:0 = 11) TCNT1 TOP Figure 46 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 46. PWM
OCRnx/TOP Update and OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
TOP ICR1 OCR1A ICR1 ICR1 ICR1 TCNT1 0xFFFF 0x0000 OCR1A OCR1A OCR1A TCNT1 TOP OCR1A TCNT1 TOV1
106
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
BOTTOM T/C TOV1 TOP OCR1A ICR1 OCR1x OC1A ICF1 TOPTOP TCNT1OCR1x TOP OCR1x "0" Figure 46 T/C TOP OCR1x OCR1x / TOP PWM TOP TOP T/C TOP TOP PWM OC1x PWM COM1x1:02PWM COM1x1:03PWM (P113 Table ) OC1x DDR_OC1x OCR1x TCNT1 OC1x PWM PWM f clk_I/O f OCnxPCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 11) COM1A1:0 = 1 OC1A 50%
107
2514I-AVR-10/03
PWM
PWM (WGM13:0 = 8 9) - PWM - PWM PWM BOTTOM TOP TOP BOTTOM TOP TCNT1 OCR1x OC1xBOTTOMTCNT1OCR1x OC1x PWM PWM OCR1x Figure 46 Figure 47 PWM PWM ICR1 OCR1A 2 (ICR1 OCR1A 0x0003) 16 (ICR1 OCR1A MAX) PWM log ( TOP + 1 ) R PFCPWM = ----------------------------------log ( 2 ) PWM ICR1 (WGM13:0 = 8) OCR1A (WGM13:0 = 9) TCNT1 TOP Figure 47 OCR1A ICR1 TOP PWM TCNT1 PWM PWM TCNT1 OCR1x TCNT1 OC1x Figure 47. PWM
OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP)
OCRnx/TOP Updateand TOVn Interrupt Flag Set (Interrupt on Bottom)
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
OCR1x T/C TOV1 TOP OCR1A ICR1 TCNT1 TOP OC1A CF1 TOP BOTTOM TOPTOP TCNT1OCR1x Figure 47 PWM OCR1x BOTTOM
108
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
PWM OC1x PWM COM1x1:0 2 PWM 3 PWM ( P112 Table ) OC1x DDR_OC1x PWM OC1x OCR1x TCNT1 ( ) ( TOP BOTTOM) ( ) TOP ICR1 TOP OCR1A OC1A PWM PWM ( TOP ) OCR1A PWM OC1x PWM COM1x1:0 2 PWM 3 PWM P113 ( Table ) OC1x PWM OC1x OCR1x TCNT1 ( ) TCNT1 ( ) PWM f clk_I/O f OCnxPFCPWM = ---------------------------2 N TOP N (1 8 64 256 1024) OCR1x PWM PWM OCR1x BOTTOM OCR1x TOP PWM OCR1A TOP (WGM13:0 = 9) COM1A1:0 = 1 OC1A 50%
109
2514I-AVR-10/03
/
/ clkT1 OCR1x OCR1x ( ) Figure 48 OCF1x Figure 48. T/C OCF1x
clkI/O clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 49 Figure 49. T/C OCF1x fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 50 TOP PWM OCR1x BOTTOM TOP BOTTOM BOTTOM+1 TOP-1 BOTTOM TOV1
110
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Figure 50. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 51 Figure 51. T/C fclk_I/O/8
clk I/O clk Tn
(clk /8) I/O
TCNTn
(CTC and FPWM)
TOP - 1 TOP - 1
TOP
BOTTOM
BOTTOM + 1
TCNTn
(PC and PFC PWM)
TOP
TOP - 1
TOP - 2
TOVn (FPWM) and ICF n (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
111
2514I-AVR-10/03
16 /
T/C1 A--TCCR1A
/ 7
COM1A1
6
COM1A0
5
COM1B1
4
COM1B0
3
-
2
-
1
WGM11
0
WGM10 TCCR1A
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R 0
R/W 0
R/W 0
* 7:6 - COM1A1:0: A * 5:4 - COM1B1:0: B COM1A1:0 COM1B1:0 OC1A OC1B COM1A1:0(COM1B1:0) "1"OC1A(OC1B) I/O OC1A(OC1B) OC1A(OC1B) COM1x1:0 WGM13:0 Table 55 WGM13:0 CTC ( PWM) COM1x1:0 . Table 55. PWM
COM1A1/COM1B1 0 0 1 1 COM1A0/COM1B0 0 1 0 1 OC1A/OC1B OC1A/OC1B OC1A/OC1B( ) OC1A/OC1B ( )
Table 56 WGM13:0 PWM COM1x1:0 Table 56. PWM(1)
COM1A1/COM1B1 0 0 COM1A0/COM1B0 0 1 OC1A/OC1B WGM13:0 = 15: OC1A OC1B WGM1 OC1A/OC1B OC1A/OC1BOC1A/OC1B TOP OC1A/OC1B OC1A/OC1B TOP
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 OC1A/OC1B / P104 " PWM "
112
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Table 57WGM13:0PWMPWMCOM1x1:0 Table 57. PWM (1)
COM1A1/COM1B1 0 0 COM1A0/COM1B0 0 1 OC1A/OC1B WGM13:0 = 9 14: OC1A OC1B WGM1 OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B OC1A/OC1B
1 1 Note:
0 1
1. OCR1A/OCR1B TOP COM1A1/COM1B1 P106 " PWM "
* 1:0 - WGM11:0: TCCR1B WGM13:2 ---- ( Table 58)T/C ( ) (CTC) (PWM) (P102 " " )
113
2514I-AVR-10/03
Table 58. (1)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Note: WGM13 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 WGM12 (CTC1) 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 WGM11 (PWM11) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 WGM10 (PWM10) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 / 8 PWM 9 PWM 10 PWM CTC 8 PWM 9 PWM 10 PWM PWM PWM PWM PWM CTC PWM PWM TOP 0xFFFF 0x00FF 0x01FF 0x03FF OCR1A 0x00FF 0x01FF 0x03FF ICR1 OCR1A ICR1 OCR1A ICR1 - ICR1 OCR1A OCR1x TOP TOP TOP TOP TOP TOP BOTTOM BOTTOM TOP TOP - TOP TOP TOV1 MAX BOTTOM BOTTOM BOTTOM MAX TOP TOP TOP BOTTOM BOTTOM BOTTOM BOTTOM MAX - TOP TOP
1. CTC1 PWM11:0 WGM12:0
/
T/C1 B--TCCR1B
7 ICNC1 R/W 0
6 ICES1 R/W 0
5 - R 0
4 WGM13 R/W 0
3 WGM12 R/W 0
2 CS12 R/W 0
1 CS11 R/W 0
0 CS10 R/W 0 TCCR1B
* 7 - ICNC1: ICNC1 ICP1 ICP1 4 4 4 * 6 - ICES1: ICP1 ICES "0" ICES1 "1" ICES1 ICR1 ICF1 ICR1 TOP ( TCCR1A TCCR1B WGM13:0 ) ICP1 * 5 - TCCR1B "0"
114
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
* 4:3 - WGM13:2: TCCR1A * 2:0 - CS12:0: 3 T/C Figure 48 Figure 49 Table 59.
CS12 0 0 0 0 1 1 1 1 CS11 0 0 1 1 0 0 1 1 CS10 0 1 0 1 0 1 0 1 (T/C ) clkI/O/1 ( ) clkI/O/8 ( ) clkI/O/64 ( ) clkI/O/256 ( ) clkI/O/1024 ( ) T1 T1
T1 1 T/C1 T/C1 C--TCCR1C
/ 7 FOC1A R/W 0 6 FOC1B R/W 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 - R 0 TCCR1C
* 7 - FOC1A: A * 6 - FOC1B: B FOC1A/FOC1BWGM13:0PWM PWM TCCR1A FOC1A/FOC1B "1" COM1x1:0 OC1A/OC1B FOC1A/FOC1B COM1x1:0 FOC1A/FOC1B OCR1A TOP CTC FOC1A/FOC1B T/C1--TCNT1H TCNT1L
7 6 5 4 3 2 1 0 TCNT1H TCNT1L R/W 0 R/W 0 R/W 0
TCNT1[15:8] TCNT1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
TCNT1HTCNT1LT/C1TCNT1 / 16 CPU 8 TEMPTEMP 16 P94 " 16 " 115
2514I-AVR-10/03
TCNT1TCNT1OCR1x TCNT1 1A--OCR1AH OCR1AL
7 6 5 4 3 2 1 0 OCR1AH OCR1AL R/W 0 R/W 0 R/W 0
OCR1A[15:8] OCR1A[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
1B--OCR1BH OCR1BL
7
6
5
4
3
2
1
0 OCR1BH OCR1BL
OCR1B[15:8] OCR1B[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0
16 TCNT1 OC1x 16 CPU 8 TEMP TEMP 16 P94 " 16 "
116
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
1--ICR1H ICR1L
7 6 5 4 ICR1[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 ICR1H ICR1L
ICR1[15:8]
ICP1(T/C1) TCNT1 ICR1 ICR1 TOP 16 CPU 8 TEMP TEMP 16 P94 " 16 " T/C1 --TIMSK1
/ 7 - R 0 6 - R 0 5 ICIE1 R/W 0 4 - R 0 3 - R 0 2 OCIE1B R/W 0 1 OCIE1A R/W 0 0 TOIE1 R/W 0 TIMSK1
* 5 - ICIE1: T/C1 "1" I "1" T/C1 T IFR1 ICF1 CPU T/C1 ( P45 " " ) * 2 - OCIE1B: T/C1 B "1" I "1" T/C1 B TIFR1 OCF1B CPU T/C1 B ( P45 " " ) * 1 - OCIE1A: T/C1 A "1" I "1" T/C1 A TIFR1 OCF1A CPU T/C1 A ( P45 " " ) * 0 - TOIE1: T/C1 "1" I "1" T/C1 TIFR1 TOV1 CPU T/C1 ( P45 " " )
117
2514I-AVR-10/03
T/C1 --TIFR1
/
7 - R 0
6 - R 0
5 ICF1 R/W 0
4 - R 0
3 - R 0
2 OCF1B R/W 0
1 OCF1A R/W 0
0 TOV1 R/W 0 TIFR1
* 5 - ICF1: T/C1 ICP1 ICF1 ICR1 TOP TOP ICF1 ICF1 "1" * 2 - OCF1B: T/C1 B TCNT1 OCR1B "1" (FOC1B) OCF1B B OCF1B "1" * 1 - OCF1A: T/C1 A TCNT1 OCR1A "1" (FOC1A) OCF1A A OCF1A "1" * 0 - TOV1: T/C1 T/C1 CTC T/C1 TOV1 TOV1 P114 Table 58 OCF1A "1"
118
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
8 PWM / 2
T/C2 8 / * * ( ) * , (PWM) * * 10 * (TOV2 OCF2A) * 32 kHz I/O Figure 52 8 T/C P2 "ATmega169 " CPU I/O I/O I/O I/O P128 "8 T/C " Figure 52. 8 T/C
TCCRnx
count clear direction Control Logic
TOVn (Int.Req.) clkTn TOSC1
BOTTOM
TOP Prescaler
T/C Oscillator TOSC2
Timer/Counter TCNTn
=0
= 0xFF
OCnx (Int.Req.) clkI/O
=
Waveform Generation
OCnx
OCRnx
DATA BUS
Synchronized Status flags
clkI/O Synchronization Unit clkASY
Status flags
ASSRn asynchronous mode select (ASn)
/ TCNT2 OCR2A 8 ( Int.Req.) TIFR2 TIMSK2 TIFR2 TIMSK2 T/C2 TOSC1/2 ASSR T/C() T/C clkT2 OCR2A TCNT2 PWM OC2A P122" " OCF2A
119
2514I-AVR-10/03
"n" / 2 (TCNT2T/C2) Table 60 Table 60. BOTTOM MAX TOP 0x00 BOTTOM 0xFF ( 255) MAX TOPTOP 0xFF (MAX) OCR2A
T/C
T/C clkT2 MCU clkI/O ASSR AS2 TOSC1 TOSC2 P131 " - ASSR" P134 " / " 8T/CFigure 53 8 T/C Figure 53.
DATA BUS
TOVn (Int.Req.)
TOSC1 count TCNTn clear direction Control Logic clk Tn Prescaler T/C Oscillator TOSC2
bottom
top
clkI/O
( ) count direction clear clkT2 top bottom TCNT2 1 1 TCNT2 ( ) T/C TCNT2 TCNT2 (0)
clkT2 clkT2 CS22:0 (CS22:0 = 0) clkT2 CPU TCNT2 CPU ( ) T/C (TCCR2A) WGM21 WGM20 OC2A P122 " " T/CTOV2WGM21:0 TOV2CPU
120
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
8 TCNT2 OCR2A TCNT2 OCR2A OCF2A OCIE2A = 1 OCF2A "1" WGM21:0 COM2A1:0 max bottom (P122 " " ) Figure 54 Figure 54.
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top bottom FOCn
Waveform Generator
OCnx
WGMn1:0
COMnx1:0
PWM OCR2A OCR2A top bottom PWM OCR2A CPU OCR2A CPU OCR2A PWM FOC2A "1" OCF2A / OC2A (COM2A1:0 OC2A ) CPU TCNT2 OCR2A TCNT2 TCNT2 TCNT2 T/C TCNT2 OCR2A TCNT2 BOTTOM OC2A OC2A FOC2A OC2A COM2A1:0 COM2A1:0 121
2514I-AVR-10/03
TCNT2
COM2A1:0 COM2A1:0 (OC2A) COM2A1:0 OC2A Figure 55 COM21:0 I/O I/O I/O COM2A1:0 I/O (DDR PORT) OC2A OC2A OC2A Figure 55.
COMnx1 COMnx0 FOCnx
Waveform Generator
D
Q
1 OCnx Pin
OCnx D Q
0
DATA BUS
PORT D Q
DDR
clk I/O
COM2A1:0 OC2A I/O OC2A (DDR) OC2A DDR_OC2A OC2A COM2A1:0 P128 "8 T/C " COM2A1:0 CTC PWM COM2A1:0 = 0 OC2A PWMP129 Table 62 PWMP129 Table 63 PWM P129 Table 64 COM2A1:0 PWM FOC2A
- T/C - (WGM21:0) (COM2A1:0) COM2A1:0 PWM PWM COM2A1:0 (P124" " ) P126 "T/C "
122
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
(WGM21:0 = 0) 8 (TOP = 0xFF) 0x00 TCNT0 T/C TOV2 TOV2 9 TOV2 CPU CTC( ) CTC (WGM21:0 = 2) OCR2A TCNT2 OCR2A OCR2A TOP CTCFigure 56 TCNT2TCNT2OCR2A TCNT2 Figure 56. CTC
OCnx Interrupt Flag Set
TCNTn
OCnx (Toggle) Period
1 2 3 4
(COMnx1:0 = 1)
OCF2A TOP TOP CTC TOP BOTTOM OCR2A TCNT2 0xFF 0x00 OCR2A CTC OC2A COM2A1:0 = 1 OC2A fOC2 = fclk_I/O/2 (OC2A = 0x00) f clk_I/O f OCnx = --------------------------------------------------2 N ( 1 + OCRnx ) N (1 8 32 64 128 256 1024) TOV2 MAX 0x00 PWM PWM (WGM21:0 = 3) PWM PWM PWM BOTTOMMAX BOTTOM OC2A TCNT2 OCR2A BOTTOM OC2A PWM PWM
123
2514I-AVR-10/03
PWM DAC ( ) PWM MAX Figure 57 TCNT0 PWM PWM TCNT2 OCR2A TCNT2 Figure 57. PWM
OCRnx Interrupt Flag Set
OCRnx Update and TOVn Interrupt Flag Set
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
MAX T/C TOV2 PWM OC2A PWM COM21:0 2 PWM 3 PWM ( P129 Table 63 ) OC2A PWM OC2A OCR2A TCNT2 ( ) ( MAX BOTTOM) ( ) PWM f clk_I/O f OCnxPWM = -----------------N 256 N (1 8 32 64 128 256 1024) OCR2A PWM OCR2A BOTTOM MAX+1OCR2AMAX COM2A1:0 OC2A (COM2A1:0 = 1) 50% OCR2 0 foc2 = fclk_I/O/2 CTC OC2A PWM PWM PWM (WGM21:0 = 1) PWM BOTTOM MAX MAX BOTTOM MAX TCNT2 OCR2A OC2A BOTTOM TCNT2 OCR2A OC2A
124
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
PWM PWM 8 MAX TCNT2 MAX Figure 58 TCNT2 PWM PWM TCNT2 OCR2A TCNT2 Figure 58. PWM
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
OCnx OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)
Period
1
2
3
BOTTOM T/C TOV2 PWM OC2A PWM COM2A1:0 2 PWM COM2A1:0 3 PWM ( P129 Table 64 ) OC2A OCR2A TCNT2 OC2A PWM PWM f clk_I/O f OCnxPCPWM = -----------------N 510 N (1 8 32 64 128 256 1024) OCR2A PWM PWM OCR2A BOTTOM OCR2A MAX PWM Figure 58 2 OCn BOTTOM * Figure 58 OCR2A MAX OCR2A MAX OCn BOTTOM T/C MAX OCn OCn
125
2514I-AVR-10/03
*
OCR2A BOTTOM OCn OCn
T/C
T/C clkT2 clkI/O T/C Figure 59 T/C PWM MAX Figure 59. T/C
clkI/O clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 60 Figure 60. T/C fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 61 ( CTC )OCF2A
126
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Figure 61. T/C OCF2A fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx
OCRnx Value
OCFnx
Figure 62 CTC OCF2A TCNT2 Figure 62. T/C CTC fclk_I/O/8
clkI/O clkTn
(clkI/O /8)
TCNTn (CTC) OCRnx
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCFnx
127
2514I-AVR-10/03
8 T/C
T/C A--TCCR2A
/ 7
FOC2A
6
WGM20
5
COM2A1
4
COM2A0
3
WGM21
2
CS22
1
CS21
0
CS20 TCCR2A
W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
* 7 - FOC2A: FOC2A WGM PWM PWM TCCR2A 1 OC2A COM2A1:0 FOC2A COM2A1:0 FOC2A OCR2ATOPCTC FOC2A 0 * 6, 3 - WGM21:0: TOP T/C (CTC) PWM Table 61 P122 " " Table 61. (1)
WGM21 (CTC2) 0 0 1 1 WGM20 (PWM2) 0 1 0 1 OCR2A TOP TOP TOV2 MAX BOTTOM MAX MAX
0 1 2 3 Note:
T/C PWM CTC PWM
TOP 0xFF 0xFF OCR2A 0xFF
1. CTC2 PWM2 WGM21:0
128
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
* 5:4 - COM2A1:0: A OC2A COM2A1:0 OC2A 1 OC2A COM2A1:0 WGM21:0 Table 62 WGM21:0 CTC COM2A1:0 Table 62. PWM
COM2A1 0 0 1 1 COM2A0 0 1 0 1 OC2A OC2A OC2A OC2A
Table 63 WGM21:0 PWM COM2A1:0 Table 63. PWM (1)
COM2A1 0 0 1 1 Note: COM2A0 0 1 0 1 OC2A OC2A TOP OC2A OC2A TOP OC2A
1. OCR2A TOP COM2A1 TOP P125" PWM "
Table 64 WGM21:0 PWM COM2A1:0 Table 64. PWM (1)
COM2A1 0 0 1 1 Note: COM2A0 0 1 0 1 OC2A OC2A OC2A OC2A OC2A
1. OCR2A TOP COM2A1 TOP P124 " PWM "
* 2:0 - CS22:0: T/C Table 65. Table 65.
CS22 0 0 0 CS21 0 0 1 CS20 0 1 0 T/C clkT2S/1 ( ) clkT2S/8 ( )
129
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Table 65.
CS22 0 1 1 1 1 CS21 1 0 0 1 1 CS20 1 0 1 0 1 clkT2S/32 ( ) clkT2S/64 ( ) clkT2S/128 ( ) clkT2S/256 ( ) clkT2S/1024 ( )
T/C --TCNT2
/
7 R/W 0
6 R/W 0
5 R/W 0
4 R/W 0
3 R/W 0
2 R/W 0
1 R/W 0
0 TCNT2 R/W 0
TCNT2[7:0]
T/C 8 TCNT2 TCNT2 TCNT2 OCR2A A--OCR2A
/ 7 R/W 0 6 R/W 0 5 R/W 0 4 R/W 0 3 R/W 0 2 R/W 0 1 R/W 0 0 OCR2A R/W 0
OCR2A[7:0]
A 8 TCNT2 OC2A
130
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
/
--ASSR
/ 7 - R 0 6 - R 0 5 - R 0 4 EXCLK R/W 0 3 AS2 R/W 0 2 TCN2UB R 0 1 OCR2UB R 0 0 TCR2UB R 0 ASSR
* 4 - EXCLK: EXCLK "1" TOSC1 32 kHz EXCLK "0" * 3 - AS2: T/C2 AS2"0"T/C2I/OclkI/OAS2"1"T/C2TOSC1 AS2 TCNT2 OCR2A TCCR2A * 2 - TCN2UB: T/C2 T/C2 TCNT2TCN2UB TCNT2 TCN2UB TCN2UB 0 TCNT2 * 1 - OCR2UB: 2 T/C2 OCR2A OCR2UB OCR2A OCR2UB OCR2UB 0 OCR2A * 0 - TCR2UB: T/C2 T/C2 TCCR2ATCR2UB TCCR2A TCR2UB TCR2UB 0 TCCR2A TCNT2 OCR2A TCCR2A TCNT2 OCR2A TCCR2A
131
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/ 2
T/C2 * : TCNT2 OCR2A TCCR2A 1. OCIE2A TOIE2 T/C2 2. AS2 3. TCNT2 OCR2A TCCR2A 4. TCN2UB OCR2UB TCR2UB 5. T/C2 6. * * 4 TCNT2 OCR2A TCCR2A TOSC1 3 TCNT2 OCR2A ASSR T/C2 MCU ADC TCNT2 OCR2ATCCR2A MCUT/C2 T/C2 MCU OCR2A TCNT2 (OCR2UB 0)MCU MCU T/C2 ADC TOSC1 TOSC1 1. TCCR2A TCNT2 OCR2A 2. ASSR 3. ADC * T/C2 32.768 kHz Standby 1 /Standby 1 T/C2 T/C2 ADC : MCU 4 SLEEP TCNT2 TCNT2 TOSC TCNT2 I/O TOSC1 I/O TCNT2 TOSC1 TOSC1 TCNT2 1. OCR2A TCCR2A 2. 3. TCNT2 * 3
*
*
*
*
132
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2514I-AVR-10/03
ATmega169V/L
/ 2 --TIMSK2
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 OCIE2A R/W 0 0 TOIE2 R/W 0 TIMSK2
* 1 - OCIE2A: T/C2 A OCIE2A I "1" T/C2 A T/C2 TIFR2 OCF2A * 0 - TOIE2: T/C2 TOIE2 I "1" T/C2 T/C2 TIFR2 TOV2 / 2 --TIFR2
/ 7 - R 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 OCF2A R/W 0 0 TOV2 R/W 0 TIFR2
* 1 - OCF2A: 2 A T/C2 OCR2A( 2) OCF2A 1 SREG I OCIE2A OCF2A * 0 - TOV2: T/C2 T/C2 TOV2 TOV2 1 SREG ITOIE2A TOV2 PWM T/C2 0x00 TOV2
133
2514I-AVR-10/03
/
Figure 63. T/C2
clkI/O TOSC1 clkT2S Clear
10-BIT T/C PRESCALER
AS2
PSR2
0
CS20 CS21 CS22
TIMER/COUNTER2 CLOCK SOURCE clkT2
T/C2 clkT2S clkT2 clkI/O ASSR AS0 T/C2 TOSC1 T/C2 RTC TOSC1 TOSC2 C ( 32.768 kHz ) TOSC1 T/C2 clkT2S/8 clkT2S/32 clkT2S/64 clkT2S/128 clkT2S/256 clkT2S/1024 clkT2S0 () GTCCRPSR2 T/C --GTCCR
/ 7 TSM R/W 0 6 - R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 PSR2 R/W 0 0 PSR10 R/W 0 GTCCR
* 1 - PSR2:T/C2 "1" T/C2 T/C2 TSM T/CP91 " 7 - TSM: T/C "
134
ATmega169V/L
2514I-AVR-10/03
clkT2S/1024
clkT2S/32
clkT2S/64
clkT2S/128
clkT2S/256
clkT2S/8
ATmega169V/L
--SPI
SPI ATmega169 AVR ATmega169 SPI * 3 * * LSB MSB * 7 * * * * (CK/2) Figure 64. SPI (1)
DIVIDER /2/4/8/16/32/64/128
SPI2X
Note:
1. SPI P2 Figure 1 P58 Table 29
SPI Figure 65 SS SCK MOSI MOSI MISO MISO SS SPI SPI SS SPI SPI 8 SPI SPIF SPCR SPI SPIE SPDR SS
SPI2X
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2514I-AVR-10/03
SS SPI MISO SPI SPDR SCK SPDR SS SPIF SPCRSPISPIE SPDR Figure 65. SPI -
SHIFT ENABLE
SPI SPI SPI SPI SCK SPI fosc/4 SPI MOSI MISO SCK SS Table 66 P55 " " Table 66. SPI (1)
MOSI MISO SCK SS Note: SPI SPI
1. P58 " B " SPI
SPI DDR_SPIDD_MOSI DD_MISODD_SCK
136
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
MOSI PB5 DD_MOSI DDB5 DDR_SPI DDRB (1)
SPI_MasterInit: ; MOSI SCK ldi out ldi out ret SPI_MasterTransmit: ; (r16) out SPDR,r16 Wait_Transmit: ; sbis SPSR,SPIF rjmp Wait_Transmit ret r17,(1<; SPI fck/16
C (1)
void SPI_MasterInit(void) { /* MOSI SCK */ DDR_SPI = (1<Note:
1.
137
2514I-AVR-10/03
SPI (1)
SPI_SlaveInit: ; MISO ldi out ldi out ret SPI_SlaveReceive: ; sbis SPSR,SPIF rjmp SPI_SlaveReceive ; in ret r16,SPDR r17,(1<; SPI
C (1)
void SPI_SlaveInit(void) { /* MISO */ DDR_SPI = (1<Note:
1.
138
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
SS
SPI SS SS SPI MISO ( ) SS SPI SS / SS SPI SPI (MSTR SPCR ) SS SS I/O SPI SS SS SPI SS SPI SPI 1. SPCR MSTR SPI MOSI SCK 2. SPSR SPIF SPI SPI SS MSTR "1" SPI SPI --SPCR
/ 7 SPIE R/W 0 6 SPE R/W 0 5 DORD R/W 0 4 MSTR R/W 0 3 CPOL R/W 0 2 CPHA R/W 0 1 SPR1 R/W 0 0 SPR0 R/W 0 SPCR
* 7 - SPIE: SPI SPSR SPIF SREG SPI * 6 - SPE: SPI SPE SPI SPI SPE * 5 - DORD: DORD LSB MSB * 4 - MSTR: / MSTR MSTR "1" SS MSTR SPSR SPIF MSTR * 3 - CPOL: CPOL SCK SCK Figure 66 Figure 67 CPOL Table 67. CPOL
CPOL 0 1
139
2514I-AVR-10/03
* 2 - CPHA: CPHA SCK SCK Figure 66 Figure 67 Table 68. CPHA
CPHA 0 1
* 1, 0 - SPR1, SPR0: SPI SCK SPR1 SPR0 SCK fosc Table 69. SCK
SPI2X 0 0 0 0 1 1 1 1 SPR1 0 0 1 1 0 0 1 1 SPR0 0 1 0 1 0 1 0 1 SCK
fosc/4 fosc/16 fosc/64 fosc/128 fosc/2 fosc/8 fosc/32 fosc/64
140
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
SPI --SPSR
/ 7 SPIF R 0 6 WCOL R 0 5 - R 0 4 - R 0 3 - R 0 2 - R 0 1 - R 0 0 SPI2X R/W 0 SPSR
* 7 - SPIF: SPI SPIF SPCR SPIE SPI SPI SS SPIF SPIF SPSR SPDRSPIF * 6 - WCOL: SPI SPDR WCOL WCOL SPSR SPDR * 5..1 - Res: * 0 - SPI2X: SPI SPI ( Table 69) SCK CPU fosc /4 ATmega169 SPI EEPROM P269 SPI SPI --SPDR
/ 7 MSB R/W X R/W X R/W X R/W X R/W X R/W X R/W X 6 5 4 3 2 1 0 LSB R/W X Undefined SPDR
SPI / SPI
141
2514I-AVR-10/03
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 66 and Figure 67. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 67 and Table 68, as done SCK 4 CPHA CPOL SPI Figure 66 Figure 67 SCK Table 67 Table 68 Table 70. CPOL
CPOL=0, CPHA=0 CPOL=0, CPHA=1 CPOL=1, CPHA=0 CPOL=1, CPHA=1 ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) SPI 0 1 2 3
Figure 66. CPHA = 0 SPI
SCK (CPOL = 0) mode 0 SCK (CPOL = 1) mode 2 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) MSB LSB first (DORD = 1) LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
Figure 67. CPHA = 1 SPI
SCK (CPOL = 0) mode 1 SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS
MSB first (DORD = 0) LSB first (DORD = 1)
MSB LSB
Bit 6 Bit 1
Bit 5 Bit 2
Bit 4 Bit 3
Bit 3 Bit 4
Bit 2 Bit 5
Bit 1 Bit 6
LSB MSB
142
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
USART
(USART) * ( ) * * * * 5, 6, 7, 8, 9 1 2 * * * * * , * * Figure 68 USART CPU I/O I/O Figure 68. USART (1)
Clock Generator
UBRR[H:L] OSC
BAUD RATE GENERATOR
SYNC LOGIC
PIN CONTROL
XCK
Transmitter
UDR (Transmit) PARITY GENERATOR TRANSMIT SHIFT REGISTER PIN CONTROL TxD TX CONTROL
DATA BUS
Receiver
CLOCK RECOVERY RX CONTROL
RECEIVE SHIFT REGISTER
DATA RECOVERY
PIN CONTROL
RxD
UDR (Receive)
PARITY CHECKER
UCSRA
UCSRB
UCSRC
Note:
1. P2 Figure 1 P64 Table 36 P60 Table 30 USART
USART : XCK ( ) 143
2514I-AVR-10/03
USART UDR AVR USART AVR UART-- USART AVR UART * USART * * * * * FIFO FE DOR 9 RXB8 UDR ( Figure 68) USART (DOR) CHR9 UCSZ2 OR DOR
*
* *
USART 4 : USART UMSEL C (UCSRC) ( ) UCSRA U2X (UMSEL = 1) XCK (DDR_XCK)()() XCK Figure 69 Figure 69.
UBRR fosc Prescaling Down-Counter UBRR+1 /2 /4 /2 U2X
0 1 0 DDR_XCK 1
OSC
txclk
xcki XCK Pin xcko
Sync Register
Edge Detector
0 1
UMSEL
DDR_XCK
UCPOL
1 0
rxclk
txclk 144 ( )
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
rxclk xcki xcko fosc -- ( ) XCK ( ) XCK ( ) XTAL ( )
Figure 69 USART UBRR UBRRL UBRR fosc/(UBRR+1) 2 8 16 2 816 UMSEL U2X DDR_XCK Table 71 ( / ) UBRR
145
2514I-AVR-10/03
Table 71.
(U2X = 0) (U2X = 1) (1) UBRR
f OSC BAUD = --------------------------------------16 ( UBRR + 1 ) f OSC BAUD = -----------------------------------8 ( UBRR + 1 ) f OSC BAUD = -----------------------------------2 ( UBRR + 1 )
f OSC UBRR = ----------------------- - 1 16BAUD f OSC UBRR = -------------------- - 1 8BAUD f OSC UBRR = -------------------- - 1 2BAUD
Note:
1. (bps)
BAUD ( bps) fOSC UBRR UBRRH UBRRL (0-4095) P169Table 79 UBRR (U2X) UCSRA U2X "0" 16 8 Figure 69 XCK CPU XCK f OSC f XCK < -----------4 fosc
146
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
(UMSEL = 1)XCK ( ) ( ) TxD XCK RxD Figure 70. XCK
UCPOL = 1 XCK RxD / TxD Sample UCPOL = 0 XCK RxD / TxD Sample
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is used for data change. As Figure 70 shows, when UCPOL is zero the data will be changed at rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at falling XCK edge and sampled at rising XCK edge. UCRSC UCPOL XCK Figure 70 UCPOL=0 XCK XCK UCPOL=1 XCK XCK
( ) USART 30 * * * * 1 5 6 7 8 9 1 2
9 Figure 71 Figure 71.
FRAME
(IDLE)
St
0
1
2
3
4
[5]
[6]
[7]
[8]
[P]
Sp1 [Sp2]
(St / IDLE)
St (n) P
(0 8)
147
2514I-AVR-10/03
Sp IDLE
(RxD TxD)
UCSRB UCSRC UCSZ2:0 UPM1:0 USBS USART UCSZ2:0 UPM1:0 USBS (FE) "0" P even = d n - 1 ... d 3 d 2 d 1 d 0 0 P odd = d n - 1 ... d 3 d 2 d 1 d 0 1 Peven Podd dn n
USART
USART USART ( ) USART TXC RXC ( UDR )TXC
148
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
USART ( ) r17:r16 (1)
USART_Init: ; out out ldi out ldi out ret UBRRH, r17 UBRRL, r16 r16, (1<;
; : 8 , 2
C (1)
void USART_Init( unsigned int baud ) { /* */ UBRRH = (unsigned char)(baud>>8); UBRRL = (unsigned char)baud; /* */ UCSRB = (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
I/O
149
2514I-AVR-10/03
--USART
UCSRB TXEN USART TxD I/O USART XCK CPU UDR ( ) UDRE 8 UDR USART R16 (1)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; out ret UDR,r16
5 8
C (1)
void USART_Transmit( unsigned char data ) { /* W */ while ( !( UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
UDRE
150
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
9 9 (UCSZ = 7) 9 UCSRB TXB8 8UDR 9 R17:R16 (1)(2)
USART_Transmit: ; sbis UCSRA,UDRE rjmp USART_Transmit ; 9 r17 TXB8 cbi sbi out ret UCSRB,TXB8 UCSRB,TXB8 UDR,r16 sbrc r17,0 ; 8
C (1)(2)
void USART_Transmit( unsigned int data ) { /* W */ while ( !( UCSRA & (1<Notes:
1. UCSRB UCSRB TXB8 2. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
9
151
2514I-AVR-10/03
USART USART UDRE TXC UDRE "1" UCSRA "0" UCSRB UDRIE "1" UDRE ( ) USART UDR UDRE UDR UDRE TXC TXC "1" TXC RS-485 UCSRB TXCIE "1" TXC USART TXC TXC

(UPM1 = 1) TXEN TxD I/O
152
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
--USART
UCSRB (RXEN) USART RxD USART XCK XCK UDR RXC 8 UDR 0 USART (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; in ret r16, UDR
5 8
C (1)
unsigned char USART_Receive( void ) { /* */ while ( !(UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
RXC
153
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9
9 (UCSZ = 7) 9 UCSRB TXB8 8UDR 9 9 (UCSZ=7) UDR 8 UCSRB RXB8 9 FE DOR UPE UCSRA UDR UDR FIFO FIFO TXB8, FE, DOR USART 9 (1)
USART_Receive: ; sbis UCSRA, RXC rjmp USART_Receive ; 9 in in in r18, UCSRA r17, UCSRB r16, UDR
; -1 andi r18,(1<USART_ReceiveNoError: ; 9 lsr ret r17 andi r17, 0x01
C (1)
unsigned int USART_Receive( void ) { unsigned char status, resh, resl; /* */ while ( !(UCSRA & (1<> 1) & 0x01; return ((resh << 8) | resl); }
Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC"
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"SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
I/O USART (RXC) 1 0( ) (RXEN = 0) RXC UCSRB ((RXCIE) RXC ( ) USART UDR RXC USART (FE) (DOR) (UPE) UCSRA UDR UCSRA (UDR) "0" (FE) ( 1) FE 0 FE 1 UCSRC USBS FE UCSRA 0 (DOR) ( ) DOR UDR UDR UCSRA 0 DOR (UPE) UPE UCSRA 0 P148 " " P156 " "
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UPM1 ( ) UPM0 (UPE) (UPM1 = 1) UPE (UDR)
(RXEN ) RxD FIFO FIFO UDR RXC (1)
USART_Flush: sbis UCSRA, RXC ret in r16, UDR rjmp USART_Flush
C (1)
void USART_Flush( void ) { unsigned char dummy; while ( UCSRA & (1<Note:
1. I/O I/O "LDS" "STS" "SBRS" "SBRC" "SBR" "CBR" I/O "IN""OUT""SBIS""SBIC" "CBI" "SBI"
USART RxD
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Figure 72 16 8 (U2X = 1) RxD ( ) 0 Figure 72.
RxD IDLE START BIT 0
Sample
(U2X = 0) 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3
Sample
(U2X = 1) 0 1 2 3 4 5 6 7 8 1 2
RxD ( ) ( ) 1 0 8 9 10( ) 4 5 6( ) ( ) 16 8 Figure 73 Figure 73.
RxD BIT n
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1
Sample
(U2X = 1) 1 2 3 4 5 6 7 8 1
2 3 1 2 3 0RxD Figure 74
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Figure 74.
RxD STOP 1
(A) (B) (C)
Sample
(U2X = 0) 1 2 3 4 5 6 7 8 9 10 0/1 0/1 0/1
Sample
(U2X = 1) 1 2 3 4 5 6 0/1
0 FE Figure 74 A B C ( Table 72) ( D + 1 )S R slow = --------------------------------------------S - 1 + D S + SF D S SF SM (D = 5 10 ) S = 16 S = 8 SF = 8 SF = 4 SM = 9 SM = 5 ( D + 2 )S R fast = ------------------------------------( D + 1 )S + S M
Rslow Rfast Table 72 Table 73
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Table 72. (U2X = 0)
D # + 5 6 7 8 9 10 Rslow (%) 93.20 94.12 94.81 95.36 95.81 96.17 Rfast (%) 106.67 105.79 105.11 104.58 104.14 103.78 (%) +6.67/-6.8 +5.79/-5.88 +5.11/-5.19 +4.58/-4.54 +4.14/-4.19 +3.78/-3.83 (%) 3.0 2.5 2.0 2.0 1.5 1.5
Table 73. (U2X = 1)
D # + 5 6 7 8 9 10 Rslow (%) 94.12 94.92 95.52 96.00 96.39 96.70 Rfast (%) 105.66 104.92 104,35 103.90 103.53 103.23 (%) +5.66/-5.88 +4.92/-5.08 +4.35/-4.48 +3.90/-4.00 +3.53/-3.61 +3.23/-3.30 (%) 2.5 2.0 1.5 1.5 1.5 1.0
(XTAL) 2% UBRR
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UCSRA (MPCM) USART CPU MPCM 5 8 9 9 (RXB8) ( 9 ) 1
MPCM
9 (UCSZ = 7) (TXB8 = 1) 9 (TXB8) 1 (TXB = 0) 9 1. (UCSRA MPCM ) 2. UCSRA RXC 3. UDR UCSRA MPCM MPCM 1 4. MPCM 1 5. MPCM 2 5 8 n n+1 5 8 (USBS = 1) - - (SBI CBI) MPCM MPCM TXC I/O SBI CBI
USART
USART I/O --UDR
7 6 5 4 RXB[7:0] TXB[7:0] / R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 3 2 1 0 UDR ( ) UDR ( )
USART USART I/O USART UDR UDR (TXB) UDR (RXB) 567 0 UCSRA UDRE UDRE UDR USART
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TxD FIFO FIFO - - (SBI CBI) (SBIC SBIS) FIFO USART A -- UCSRA
/ 7 RXC R 0 6 TXC R/W 0 5 UDRE R 1 4 FE R 0 3 DOR R 0 2 UPE R 0 1 U2X R/W 0 0 MPCM R/W 0 UCSRA
* 7 - RXC: USART RXC RXC RXC ( RXCIE ) * 6 - TXC: USART (UDR) TXC TXC 1 TXC ( TXCIE ) * 5 - UDRE: USART UDRE(UDR) UDRE1 UDRE ( UDRIE ) UDRE * 4 - FE: 0 FE (UDR) 1 FE 0 UCSRA 0 * 3 - DOR: DOR ( ) (UDR) UCSRA 0 * 2 - UPE: USART (UPM1 = 1) UPE (UDR) UCSRA 0 * 1 - U2X: 1 16 8
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* 0 - MPCM: MPCM USART MPCM P160 " "
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USART B -- UCSRB
/ 7 RXCIE R/W 0 6 TXCIE R/W 0 5 UDRIE R/W 0 4 RXEN R/W 0 3 TXEN R/W 0 2 UCSZ2 R/W 0 1 RXB8 R 0 0 TXB8 R/W 0 UCSRB
* 7 - RXCIE: RXC RXCIE 1 SREG UCSRA RXC 1 USART * 6 - TXCIE: TXC TXCIE 1 SREG UCSRA TXC 1 USART * 5 - UDRIE: USART UDRE UDRIE 1 SREG UCSRA UDRE 1 USART * 4 - RXEN: USART RxD USART FE DOR UPE * 3 - TXEN: USART TxD USART TXEN TxD I/O * 2 - UCSZ2: UCSZ2UCSRCUCSZ1:0( ) * 1 - RXB8: 8 9 RXB8 9 UDR RXB8 * 0 - TXB8: 8 9 TXB8 9 UDR
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USART C-- UCSRC
/
7 - R 0
6 UMSEL R/W 0
5 UPM1 R/W 0
4 UPM0 R/W 0
3 USBS R/W 0
2 UCSZ1 R/W 1
1 UCSZ0 R/W 1
0 UCPOL R/W 0 UCSRC
* 6 - UMSEL: USART Table 74. UMSEL
UMSEL 0 1
* 5:4 - UPM1:0: UPM0 UCSRA UPE Table 75. UPM
UPM1 0 0 1 1 UPM0 0 1 0 1
* 3 - USBS: Table 76. USBS
USBS 0 1 1 2
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* 2:1 - UCSZ1:0: UCSZ1:0UCSRB UCSZ2( ) Table 77. UCSZ
UCSZ2 0 0 0 0 1 1 1 1 UCSZ1 0 0 1 1 0 0 1 1 UCSZ0 0 1 0 1 0 1 0 1 5 6 7 8 9
* 0 - UCPOL: UCPOL XCK Table 78. UCPOL
UCPOL 0 1 (TxD ) XCK XCK (RxD ) XCK XCK
USART-- UBRRL UBRRH
15 - 7
14 - 6 R R/W 0 0
13 - 5 R R/W 0 0
12 -
11
10
9
8 UBRRH UBRRL 0 R/W R/W 0 0
UBRR[11:8] 3 R/W R/W 0 0 2 R/W R/W 0 0 1 R/W R/W 0 0
UBRR[7:0] 4 R R/W 0 0 / R R/W 0 0
* 15:12 - UBRRH * 11:0 - UBRR11:0: USART 12 USART UBRRH USART 4 UBRRL 8 UBRRL
Table 79 UBRR 0.5%
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( P158 " " )
BaudRate Closest Match Error[%] = ------------------------------------------------------- - 1 * 100% BaudRate
Table 79. UBRR
fosc = 1.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k (1) 1. U2X = 0 UBRR 25 12 6 3 2 1 1 0 - - - - 0.2% 0.2% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - - - U2X = 1 UBRR 51 25 12 8 6 3 2 1 1 0 - - 125 kbps 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - fosc = 1.8432 MHz U2X = 0 UBRR 47 23 11 7 5 3 2 1 1 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -25.0% 0.0% - - U2X = 1 UBRR 95 47 23 15 11 7 5 3 2 1 0 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% - fosc = 2.0000 MHz U2X = 0 UBRR 51 25 12 8 6 3 2 1 1 0 - - 125 kbps 0.2% 0.2% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% -18.6% 8.5% - - U2X = 1 UBRR 103 51 25 16 12 8 6 3 2 1 - 0 250 kbps 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% - 0.0%
62.5 kbps UBRR = 0, = 0.0%
115.2 kbps
230.4 kbps
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Table 80. UBRR ( )
fosc = 3.6864 MHz (bps)) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 4.0000 MHz U2X = 1 U2X = 0 UBRR 103 51 25 16 12 8 6 3 2 1 0 0 - - 250 kbps 0.2% 0.2% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 8.5% 8.5% 0.0% - - U2X = 1 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -
fosc = 7.3728 MHz U2X = 0 UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - U2X = 1 UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8%
U2X = 0 UBRR 95 47 23 15 11 7 5 3 2 1 0 0 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - -
UBRR 191 95 47 31 23 15 11 7 5 3 1 1 0 -
230.4 kbps UBRR = 0, = 0.0%
460.8 kbps
0.5 Mbps
460.8 kbps
921.6 kbps
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Table 81. UBRR ( )
fosc = 8.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 11.0592 MHz U2X = 0 UBRR 287 143 71 47 35 23 17 11 8 5 2 2 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 575 287 143 95 71 47 35 23 17 11 5 5 2 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% - -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% UBRR 383 191 95 63 47 31 23 15 11 7 3 3 1 0
fosc = 14.7456 MHz U2X = 0 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% -7.8% -7.8% U2X = 1 UBRR 767 383 191 127 95 63 47 31 23 15 7 6 3 1 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 5.3% -7.8% -7.8%
U2X = 0 UBRR 207 103 51 34 25 16 12 8 6 3 1 1 0 - 0.2% 0.2% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% -7.0% 8.5% 8.5% 0.0% 0.0% -
U2X = 1 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0
0.5 Mbps UBRR = 0, = 0.0%
1 Mbps
691.2 kbps
1.3824 Mbps
921.6 kbps
1.8432 Mbps
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Table 82. UBRR ( )
fosc = 16.0000 MHz (bps) 2400 4800 9600 14.4k 19.2k 28.8k 38.4k 57.6k 76.8k 115.2k 230.4k 250k 0.5M 1M 1.
(1)
fosc = 18.4320 MHz U2X = 0 UBRR 479 239 119 79 59 39 29 19 14 9 4 4 - - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% -7.8% - - U2X = 1 UBRR 959 479 239 159 119 79 59 39 29 19 9 8 4 - 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 0.0% 2.4% -7.8% - 0.0% -0.1% 0.2% -0.1% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% -3.5% 0.0% 0.0% 0.0% UBRR 520 259 129 86 64 42 32 21 15 10 4 4 - -
fosc = 20.0000 MHz U2X = 0 0.0% 0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% 1.7% -1.4% 8.5% 0.0% - - U2X = 1 UBRR 1041 520 259 173 129 86 64 42 32 21 10 9 4 - 0.0% 0.0% 0.2% -0.2% 0.2% -0.2% 0.2% 0.9% -1.4% -1.4% -1.4% 0.0% 0.0% -
U2X = 0 UBRR 416 207 103 68 51 34 25 16 12 8 3 3 1 0 -0.1% 0.2% 0.2% 0.6% 0.2% -0.8% 0.2% 2.1% 0.2% -3.5% 8.5% 0.0% 0.0% 0.0% 1 Mbps UBRR = 0, = 0.0%
U2X = 1 UBRR 832 416 207 138 103 68 51 34 25 16 8 7 3 1
2 Mbps
1.152 Mbps
2.304 Mbps
1.25 Mbps
2.5 Mbps
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--USI
T USI USI USI * ( , fSCLmax = fCK/16) * ( fSCKmax = fCK/4) * * * * Figure 75.USI I/OP2 "ATmega169" CPU I/O I/O P176 "USI " Figure 75.
DQ LE
DO (Output only)
DI/SDA
Bit7 Bit0
(Input/Open Drain)
USIDR
3 2 1 0 TIM0 COMP
USIOIF
USISIF
USIDC
USIPF
4-bit Counter
3 2 1 0 [1]
0 1
CLOCK HOLD
USCK/SCL
(Input/Open Drain)
DATA BUS
USISR
Two-wire Clock Control Unit
2
USIWM1
USIWM0
USICS1
USICS0
USICLK
USIOIE
USISIE
USICR
8 (DI) 4 USCK / 0
USI(SPI)01 (SS) DI DO USCK
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USITC
ATmega169V/L
Figure 76.
DO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DI
USCK SLAVE
DO
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DI
USCK PORTxn MASTER
Figure 76 USI 8 USCK USI 4 ( ) USIOI USCK USICR USITC Figure 77.
CYCLE USCK USCK DO DI
MSB MSB 6 6 5 5 4 4 3 3 2 2 1 1 LSB LSB
( Reference ) 1 2 3 4 5 6 7 8
A
B
C
D
E
Figure 77. USCK USI (USIDR) USCK 0(USICS0 = 0) DI DO ( ) 1(USICS0 = 1) 0 USI SPI 0 1 Figure 77. 1. A B
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C USCK 4 0 2. USCK (C D) (DI) USI (C) (D) 4 3. ( ) 2 8 4. 8 (16 ) SPI USI SPI
SPITransfer: sts ldi sts ldi sts lds sbrs rjmp lds ret USIDR,r16 r16,(1<SPITransfer_loop:
8 (+ ret) DO USCK DDRE r16 r16 USI USI USITC USCK 16
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(fsck = fck/4) USI SPI
SPITransfer_Fast: sts ldi ldi sts sts sts sts sts sts sts sts sts sts sts sts sts sts sts sts lds ret USIDR,r16 r16,(1<SPI
USI SPI
init: ldi sts ... SlaveSPITransfer: sts ldi sts lds sbrs rjmp lds ret USIDR,r16 r16,(1<SlaveSPITransfer_loop:
8 (+ ret) DO USCK DDRE r16 r16 USI
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USI IC (TWI) SCL SDA Figure 78.
VCC
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDA
SCL
HOLD SCL
Two-wire Clock Control Unit SLAVE
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SDA
SCL PORTxn MASTER
Figure 78 USI SCL SCL PORT USCK TWI Figure 79.
SDA SCL
S 1-7 ADDRESS 8 R/W 9 ACK 1-8 DATA 9 ACK 1-8 DATA 9 ACK P
A
B
C
D
E
F
(Figure 79.) 1. SCL (A) SDA SDA 7 0 PORT 0
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(Figure 80.) USISIF 2. SCL (B) SCL 3. SCL (C) SCL 4. ()8 SCL (D) SCL 5. SCL ( SCL(D) 14) SDA R/W R/W 1 ( SDA ) (E) SCL 6. (F) Figure 80.
USISIF DQ SDA
CLR CLR
DQ
CLOCK HOLD
SCL Write( USISIF)
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Figure 80. SDA (50 300 ns) SCL SCL CKSEL ( P23 " " ) 176 USISIF
USI
4 12 /
USI UART 4 USI 4 / 0 12 (F) USICS1
USI
USI --USIDR
/ 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 USIDR
USI USIDR USICS1..0 / 0 USICLK (USIWM1..0 = 0) (DI/SDA) (USCK/SCL) (DO SDA ) ( 7) (USICS1 = 1) ( ) (USICS1 = 0) MSB USI --USISR
/ 7
USISIF
6
USIOIF
5
USIPF
4
USIDC
3
USICNT3
2
USICNT2
1
USICNT1
0
USICNT0 USISR
R/W 0
R/W 0
R/W 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
* 7 - USISIF: USISIF (USICSx = 0b11 & USICLK = 0) (USICS = 0b10 & USICLK = 0) SCK
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USISIF USICR USISIE USISIF 1 USCL * 6 - USIOIF: 4(150) USICRUSIOIE USIOIF 1 SCL * 5 - USIPF: USIPF USIOIF 1 * 4 - USIDC: 7 USIDC * 3..0 - USICNT3..0: 4 CPU / 0 USICLK USITC USICS1..0 USITC (USICS1 = 1) USICLK 1 (USIWM1..0 = 0) (USCK/SCL) USI --USICR
/ 7 USISIE R/W 0 6 USIOIE R/W 0 5 USIWM1 R/W 0 4 USIWM0 R/W 0 3 USICS1 R/W 0 2 USICS0 R/W 0 1 USICLK W 0 0 USITC W 0 USICR
* 7 - USISIE: 1 USISIE 176 USISIF * 6 - USIOIE: . 1 USIOIE 177 USIOIF * 5..4 - USIWM1..0: USIWM1..0 USI Table 83 177
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Table 83. USIWM1..0 USI
USIWM1 0 0 USIWM0 0 1 . DO DI USCK (DO) IO DDR PORT (DI) (USCK) PORT USICR USITC SDA (DI) SCL (USCK) (1) (SDA) (SCL) DDR SDA PORT 0 SDA SDA ( ) SCL PORT 0 SCL SCL SCL (USISIF) SDA SCL SDA SCL SDA SCL SCL (USIOIF)
1
0
1
1
Note:
1. USCK (SDA) (SCL ) DI
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* 3..2 - USICS1..0: (USCK/SCL) (DI/SDA) / 0 USICS1..0 0 USICLK 1 (USICS1 = 1) USICLK USITC Table 84 USICS1..0 USICLK 4 Table 84. USICS1..0 USICLK
USICS1 0 0 0 1 1 1 1 USICS0 0 0 1 0 1 0 1 USICLK 0 1 X 0 0 1 1 (USICLK) / 0 4 (USICLK) / 0 (USITC) (USITC)
* 1 - USICLK: USICS1..0 0 USICLK 0 (USICS1 = 1) USICLK USICLK USITC 4 ( Table 84) * 0 - USITC: USITC USCK/SCL 01 DDRE4 0 (USICS1 = 1) USICLK 1 USITC 4
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AIN0 AIN1 AIN0 AIN1 ACO / 1 Figure 81 Figure 81. (2)
BANDGAP REFERENCE ACBG
ACME ADEN ADC MULTIPLEXER OUTPUT (1)
Notes:
1. P182 Table 86 2. P2 Figure 1 P58Table 28
ADC B-- ADCSRB
/
7 - R 0
6 ACME R/W 0
5 - R 0
4 - R 0
3 - R 0
2 ADTS2 R/W 0
1 ADTS1 R/W 0
0 ADTS0 R/W 0 ADCSRB
* 6 - ACME: 1 ADC (ADCSRA ADEN 0) ADC 0 AIN1 P183 " " -- ACSR
7 ACD R/W 0 6 ACBG R/W 0 5 ACO R N/A 4 ACI R/W 0 3 ACIE R/W 0 2 ACIC R/W 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR
* 7 - ACD: ACD ACD ACSR ACIE ACD * 6 - ACBG: ACBG AIN0 P41 " "
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* 5 - ACO: ACO 1-2 * 4 - ACI: ACIS1 ACIS0 ACI ACIE SREG I ACI ACI 1 * 3 - ACIE: ACIE 1 I * 2 - ACIC: ACIC / 1 T/C1 ACIC 0 T/C1 TIMSK1 ICIE1 * 1, 0 - ACIS1, ACIS0: Table 85 Table 85. ACIS1/ACIS0
ACIS1 0 0 1 1 ACIS0 0 1 0 1
ACIS1/ACIS0 ACSR
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ADC7..0 ADC ADC (ADCSRB ACME) ADC (ADCSRA ADEN 0) ADMUX MUX2..0 Table 86 ACME 0 ADEN AIN1 Table 86.
ACME 0 1 1 1 1 1 1 1 1 1 ADEN x 1 0 0 0 0 0 0 0 0 MUX2..0 xxx xxx 000 001 010 011 100 101 110 111 AIN1 AIN1 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7
1--DIDR1
/
7 - R 0
6 - R 0
5 - R 0
4 - R 0
3 - R 0
2 - R 0
1 AIN1D R/W 0
0 AIN0D R/W 0 DIDR1
* 1, 0 - AIN1D, AIN0D: AIN1, AIN0 AIN1D AIN0D 1 AIN1/0 PIN 0 AIN1/0 AIN1/0 AIN1D AIN0D
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ATmega169V/L
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ATmega169V/L
* * * * * * * * * * * * *
10 0.5 LSB 2 LSB 13 s - 260 s (50kHz 1MHz ADC ) (200kHz ADC ) 15 kSPS 8 ADC 0 - VCC ADC 1.1V ADC ADC ADC
ATmega169 10 ADC ADC 8 A 8 0V (GND) ADC ADC ADC Figure 82 ADCAVCC AVCCVCC 0.3V P190 "ADC " 1.1V AVCC AREF
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Figure 82.
ADC CONVERSION COMPLETE IRQ
INTERRUPT FLAGS ADTS[2:0]
8-BIT DATA BUS
ADIF ADIE
15 ADC DATA REGISTER (ADCH/ADCL)
ADPS0 ADC[9:0]
0
ADC MULTIPLEXER SELECT (ADMUX)
ADLAR REFS1 MUX2 MUX1 MUX4 REFS0 MUX3 MUX0
ADC CTRL. & STATUS REGISTER (ADCSRA)
ADATE ADPS2 ADPS1 ADEN
ADSC
ADIF
TRIGGER SELECT MUX DECODER
CHANNEL SELECTION
PRESCALER
GAIN SELECTION
START
CONVERSION LOGIC
AVCC
INTERNAL REFERENCE AREF
10-BIT DAC
SAMPLE & HOLD COMPARATOR +
GND
BANDGAP REFERENCE
ADC7
SINGLE ENDED / DIFFERENTIAL SELECTION
ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 + POS. INPUT MUX
ADC MULTIPLEXER OUTPUT
DIFFERENTIAL AMPLIFIER
NEG. INPUT MUX
ADC 10 GND AREF 1 LSB ADMUX REFSn AVCC 1.1V AREF AREF ADMUXMUX ADC GND ADC ADCSRA ADEN ADC ADEN ADEN ADC ADC ADC10 ADCADCHADCL ADMUX ADLAR 8 ADCH ADCL ADCH ADCL ADC ADCL ADCH ADC ADCH ADC ADCH ADCL ADC ADCHADCLADC
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ATmega169V/L
ADC ADSC 1 ADC ADC ADCSRAADCADATE ADCSRB ADC ADTS ( ADTS ) ADC 0 Figure 83. ADC
ADTS[2:0] PRESCALER
START ADIF SOURCE 1 . . . . SOURCE n ADSC ADATE
CLKADC
CONVERSION LOGIC EDGE DETECTOR
ADC ADC ADC ADC ADCSRA ADSC 1 ADC ADC ADIF ADCSRA ADSC ADSC ADSC 1
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ADC
Figure 84. ADC
ADEN START CK Reset 7-BIT ADC PRESCALER
ADPS0 ADPS1 ADPS2
ADC CLOCK SOURCE
50 kHz 200 kHz 10 200 kHz ADC 100 kHz CPU ADC ADCSRA ADPS ADCSRA ADEN ADC ADEN 1 ADEN ADCSRA ADSC ADC 13 ADC ADC (ADCSRA ADEN ) 25 ADC ADC 1.5 ADC ADC 13.5 ADC ADC ADC ADIF ADSC ( ) ADSC ADC 2 ADC 3 CPU ADC 25 ADC ADC ADSC 1 Table 87
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CK/128
CK/16
CK/32
CK/64
CK/2
CK/4
CK/8
ATmega169V/L
Figure 85. ADC ( )
First Conversion Next Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock ADEN ADSC ADIF ADCH ADCL Sign and MSB of Result LSB of Result
MUX and REFS Update
Sample & Hold
Conversion Complete
MUX and REFS Update
Figure 86. ADC
One Conversion Next Conversion
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete
MUX and REFS Update
Figure 87. ADC
One Conversion Next Conversion
Cycle Number ADC Clock Trigger Source ADATE ADIF ADCH ADCL
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
Sign and MSB of Result LSB of Result Sample & Hold MUX and REFS Update Conversion Complete Prescaler Reset
Prescaler Reset
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Figure 88. ADC
One Conversion 11 12 13 Next Conversion 1 2 3 4
Cycle Number ADC Clock ADSC ADIF ADCH ADCL
Sign and MSB of Result LSB of Result
Conversion Complete
Sample & Hold MUX and REFS Update
Table 87. ADC
& ( ) 14.5 1.5 2 ( ) 25 13 13.5
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ATmega169V/L
ADMUXMUXnREFS1:0 CPU ADC (ADCSRA ADIF ) ADSC ADSC ADC ADMUX ADMUX ADATE ADEN ADMUX ADMUX 1. ADATE ADEN 0 2. ADC 3. ADMUX ADC ADC ADSC ADC ADSC ADC ADC ADC(VREF)ADC VREF 0x3FF VREF AVCC 1.1V AREF AVCC ADC 1.1V(VBG) AREF ADC AREF VREF AREF VREF AREF AREF AVCC 1.1V ADC
ADC
ADC CPUI/O ADC 1. ADC ADC 2. ADC ( ) CPU ADC 3. ADC ADCCPU ADC ADC CPU ADC ADC CPU
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ADC ADC ADEN
190
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ATmega169V/L
Figure 89. ADC ADCn ADC ( ) (S/H) ADC10 k S/H S/H (fADC/2) ADC Figure 89.
IIH ADCn 1..100 k CS/H= 14 pF IIL VCC/2
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(EMI) 1. 2. Figure 90 AVCC LC VCC 3. ADC CPU 4. ADC Figure 90. ADC
PA0 VCC GND (ADC7) PF7 (ADC6) PF6 (ADC5) PF5 (ADC4) PF4 (ADC3) PF3 (ADC2) PF2 (ADC1) PF1 (ADC0) PF0
10
51 52 53 54 55 56 57 58 59 60 61 62 63 64 1
AREF GND AVCC
100nF Analog Ground Plane
192
ATmega169V/L
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LCDCAP
ATmega169V/L
ADC n ADC GND VREF 2n (LSBs) 0 2n-1 * (0x000 0x001) (0.5 LSB) 0 LSB
Figure 91.
Output Code
Ideal ADC Actual ADC
Offset Error
VREF Input Voltage
*
(0x3FE 0x3FF) ( 1.5 LSB) 0 LSB
Figure 92.
Output Code Gain Error
Ideal ADC Actual ADC
VREF Input Voltage
*
(INL) INL0 LSB
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Figure 93. (INL)
Output Code
*
(DNL) ( ) (1 LSB) 0 LSB
INL
Ideal ADC Actual ADC VREF Input Voltage
Figure 94. (DNL)
Output Code 0x3FF
1 LSB
DNL
0x000 0 VREF Input Voltage
* *
(1 LSB) 0.5 LSB ( ) 0.5 LSB
194
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ATmega169V/L
ADC
(ADIF ) ADC (ADCL, ADCH) V IN 1024 ADC = -------------------------V REF VIN VREF ( P196 Table 89 P197 Table 90 ) 0x000 0x3FF 1LSB
( V POS - V NEG ) 512 ADC = ------------------------------------------------------V REF Figure 95.
Output Code 0x1FF
0x000 - VREF 0x3FF 0 VREF Differential Input Voltage (Volts)
0x200
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Table 88.
VADCn VADCm + VREF VADCm + 511/512 VREF VADCm + ... VADCm + /512 VREF VADCm VADCm - 1/512 VREF ... VADCm 511 1 510
0x1FF 0x1FF 0x1FE ... 0x001 0x000 0x3FF ... /512 VREF 0x201 0x200
511 511 510 ... 1 0 -1 ... -511 -512
/512 VREF
VADCm - VREF
ADMUX = 0xFB (ADC3 - ADC2, 1.1V ) ADC3 300 mV ADC2 500 mV. ADCR = 512 * (300 - 500) / 1100 = -93 = 0x3A3. ADCL 0xC0 ADCH 0xD8 ADLAR 0 ADCL = 0xA3 ADCH = 0x03 ADC -- ADMUX
/ 7 REFS1 R/W 0 6 REFS0 R/W 0 5 ADLAR R/W 0 4 MUX4 R/W 0 3 MUX3 R/W 0 2 MUX2 R/W 0 1 MUX1 R/W 0 0 MUX0 R/W 0 ADMUX
* 7:6 - REFS1:0: Table 89 (ADCSRA ADIF ) AREF Table 89. ADC
REFS1 0 0 1 1 REFS0 0 1 0 1 AREF Vref AVCC AREF 1.1V AREF
* 5 - ADLAR: ADC ADLARADCADC ADLAR ADLAR ADC P200 "ADC - ADCL ADCH"
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ATmega169V/L
* 4:0 - MUX4:0: ADC Table 90 (ADCSRA ADIF ) Table 90.
MUX4..0 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 1.1V (VBG) 0V (GND) N/A ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 N/A ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC1 ADC2 ADC2 ADC2 ADC2 ADC2 ADC2 ADC0 ADC1 ADC2 ADC3 ADC4 ADC5 ADC6 ADC7 N/A
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ADC A-- ADCSRA

7 ADEN R/W 0
6 ADSC R/W 0
5 ADATE R/W 0
4 ADIF R/W 0
3 ADIE R/W 0
2 ADPS2 R/W 0
1 ADPS1 R/W 0
0 ADPS0 R/W 0 ADCSRA
* 7 - ADEN: ADC ADENADC ADC ADC * 6 - ADSC: ADC ADSC ADC ADSC ( ADC ADSC ADC ADSC) 25 ADC 13 ADC ADSC1 ADSC * 5 - ADATE: ADC ADATE ADC ADC ADCSRB ADC ADTS * 4 - ADIF: ADC ADC ADIF ADIE SREG I ADC ADIF 1 ADIF ADCSRA SBI CBI * 3 - ADIE: ADC ADIE SREG I ADC
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* 2:0 - ADPS2:0: ADC XTAL ADC Table 91. ADC
ADPS2 0 0 0 0 1 1 1 1 ADPS1 0 0 1 1 0 0 1 1 ADPS0 0 1 0 1 0 1 0 1 2 2 4 8 16 32 64 128
ADC --ADCL ADCH ADLAR = 0
15 - ADC7 7 R R 0 0 14 - ADC6 6 R R 0 0 13 - ADC5 5 R R 0 0 12 - ADC4 4 R R 0 0 11 - ADC3 3 R R 0 0 10 - ADC2 2 R R 0 0 9 ADC9 ADC1 1 R R 0 0 8 ADC8 ADC0 0 R R 0 0 ADCH ADCL
ADLAR = 1
15 ADC9 ADC1 7 R R 0 0 14 ADC8 ADC0 6 R R 0 0 13 ADC7 - 5 R R 0 0 12 ADC6 - 4 R R 0 0 11 ADC5 - 3 R R 0 0 10 ADC4 - 2 R R 0 0 9 ADC3 - 1 R R 0 0 8 ADC2 - 0 R R 0 0 ADCH ADCL
ADC ADCL ADC ADCH 8 ADCH ADCLADCH ADMUX ADLAR MUXn ADLAR 1 ( ) * ADC9:0: ADC ADC P196 "ADC " ADC B-- ADCSRB
7 - 6 ACME 5 - 4 - 3 - 2 ADTS2 1 ADTS1 0 ADTS0 ADCSRB
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R 0
R/W 0
R 0
R 0
R 0
R/W 0
R/W 0
R/W 0
* 7 - Res: . ADCSRB 0 * 2:0 - ADTS2:0: ADC ADCSRA ADATE ADTS ADC ADTS ADC ADCSRA ADEN 1 ADC (ADTS[2:0]=0) ADC Table 92. ADC
ADTS2 0 0 0 0 1 1 1 1 ADTS1 0 0 1 1 0 0 1 1 ADTS0 0 1 0 1 0 1 0 1 0 / 0 / 0 / B / 1 / 1
0--DIDR0
/ e
7 ADC7D R/W 0
6 ADC6D R/W 0
5 ADC5D R/W 0
4 ADC4D R/W 0
3 ADC3D R/W 0
2 ADC2D R/W 0
1 ADC1D R/W 0
0 ADC0D R/W 0 DIDR0
* 7..0 - ADC7D..ADC0D: ADC7..0 1 ADC PIN 0 ADC7..0 1
200
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
LCD
LCD / (LCD) 25 * * * * * * * * * * * * *
25 4 1/21/3 1/4 1/21/3 LCD LCD , VCC LCD ( ) 2.6 3.35V LCD LCD LCD I/O
Figure 96 LCD / I/O P2 "ATmega169 " LCD ( )
LCD Table 93 Table 93.
LCD ( ) 1/( LCD ) 1/( LCD -1) LCD
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Figure 96. LCD
clki/o TOSC 0 1 lcdcs clkLCD 12-bit Prescaler
clkLCD/4096 clkLCD/2048 clkLCD/1024 clkLCD/256 clkLCD/128 clkLCD/512 clkLCD/64 clkLCD/16
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
LCDFRR
lcdps2:0
Clock Multiplexer
D A T A B U S
LCDCRA lcdcd2:0 Divide by 1 to 8
SEG8 SEG9 SEG10 SEG11 clkLCD_PS LCD Timing Analog Switch Array SEG12 SEG13 SEG14 SEG15 SEG16 SEG17
LCDCRB
LCDDR 18 -15
SEG18 SEG19 SEG20 LATCH array 25 x 4:1 MUX LCD Ouput Decoder LCD_voltage_ok SEG21 SEG22 SEG23 VLCD 2/3 VLCD LCD Buffer/ Driver 1/2 VLCD 1/3 VLCD SEG24 COM0 COM1 COM2 COM3
LCDDR 13 -10
LCDDR 8 - 5
LCDDR 3 - 0
LCDCCR
lcdcc3:0
Contrast Controller/ Power Supply
LCD CAP
LCD
LCD clkLCD clkI/O LCDCRB LCDCS 1 TOSC1 LCD LCD
LCD
12 8 LCDPS2:0 clkLCD 1664 128 256 512 1024 2048 4096 LCDCD2:0 1 8 clkLCD_PS LCD LCD
LCD
I/O I/O 1 COM SEG LCD (1/2 ) (1/3 ) COM0 COM0 COM0 COM COM0 P204 " " LCDDR3 - LCDDR0 LCD COM1 LCDDR8 - LCDDR5
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ATmega169V/L
LCD / LCDCAP (VLCD) LCD LCD V 2.6V 3.35V VCC VLCD LCD Figure 97 ( > 470 nF) LCDCAP VLCD VLCD LCD (VLCD) Figure 97. LCDCAP
62 63 64 1 LCDCAP 2 3
LCD
/ 10 mV LCD
LCD Figure 98 SEG0 - COM0 SEG1 - COM0 Figure 98. LCDl
VLCD SEG0 GND VLCD COM0 GND VLCD GND -VLCD
Frame Frame Frame Frame
VLCD SEG1 GND VLCD COM0 GND
SEG0 - COM0
GND
SEG1 - COM0
1/2 1/2
LCD(1/2 ) 1/3 LCD 1/2 Figure 99 SEG0 - COM0 SEG1 - COM0
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Figure 99. LCD
VLCD SEG0 GND VLCD 2VLCD GND VLCD 2VLCD GND VLCD 2 -VLCD
Frame Frame
VLCD SEG0 GND VLCD VLCD 2 GND VLCD 2VLCD GND VLCD 2 -VLCD
Frame Frame
1/
COM0
1/
COM1
1/ -1/
1/
SEG0 - COM0
-1/
SEG0 - COM1
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ATmega169V/L
1/3 1/3 LCD(1/3 ) 1/3 Figure 100 SEG0 COM0 SEG1 - COM0 Figure 100. 3 LCD
VLCD 2/ V 3 LCD 1/ V 3 LCD GND VLCD 2/ V 3 LCD 1/ V 3 LCD GND VLCD 2/ V 3 LCD 1/ V 3 LCD GND -1/3VLCD -2/3VLCD -VLCD VLCD
2/ 3VLCD 3VLCD
SEG0
1/
SEG0
GND VLCD
2/
COM0
3VLCD 3VLCD
1/
COM1
GND VLCD 3VLCD 1/ V 3 LCD GND -1/3VLCD -2/3VLCD -VLCD
2/
SEG0 - COM0
SEG0 - COM1
Frame
Frame
Frame
Frame
1/4 1/3
1/3 LCD(1/4 ) Figure 101 SSEG0 COM0 SEG1 - COM0 Figure 101. 4 LCD
VLCD 2/ V 3 LCD 1/ V 3 LCD GND VLCD 2/ V 3 LCD 1/ V 3 LCD GND VLCD 2/ V 3 LCD 1/ V 3 LCD GND -1/3VLCD -2/3VLCD -VLCD VLCD
2/ 3VLCD 3VLCD
SEG0
1/
SEG0
GND VLCD
2/
COM0
3VLCD 3VLCD
1/
COM1
GND VLCD
2/ 1/ 3VLCD 3VLCD
SEG0 - COM0
Frame
Frame
GND -1/3VLCD -2/3VLCD -VLCD
SEG0 - COM1
Frame
Frame
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LCDAB 1 1/3 1/3 Figure 102 Figure 102.
VLCD 2/ V 3 LCD 1/ V 3 LCD GND VLCD 2/ V 3 LCD 1/ V 3 LCD GND VLCD 2/ V 3 LCD 1/ V 3 LCD GND -1/3VLCD -2/3VLCD -VLCD VLCD
2/ 3VLCD 3VLCD
SEG0
1/
SEG0
GND VLCD
2/
COM0
3VLCD 3VLCD
1/
COM0
GND VLCD 3VLCD 1/ V 3 LCD GND -1/3VLCD -2/3VLCD -VLCD
2/
SEG0 - COM0
SEG0 - COM0
Frame
Frame
Frame
Frame
LCD (LCDCS = 0) LCD RC LCDCS 1 TOSC1 LCD ADCLCD ASSR EXCLK 1(TOSC1) 32kHz P131 " / " LCD Standby ADC LCD P210 " LCD"
LCDBL LCD GND LCD LCD 25 LCD Table 95
LCD
LCD LCD LCD LCD
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ATmega169V/L
Figure 103.
LCD
2a
1b
2f
2b
2g
1c
2e
2c
2d
COM0
COM1
50
51
COM2
49 COM3 48 SEG0 47 SEG2 SEG1 SEG0 2f 2c 1b,1c COM0 2g 2d 2a COM1 .. 2e 2b COM2 SEG1 46 SEG2 45
ATmega169
Connection table
: :
TN 3 21 1/3 1/3 3.3 0.9 V
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(1)
LCD_Init: ; 32 kHz ; 1/3 1/3 , SEG21:SEG24 ldi sts r16, (1<; 16 7 LCD ; 49 Hz ldi sts r16, (1<; 3.3 V ldi sts r16, (1<; LCD ldi sts ret r16, (1<C (1)
Void LCD_Init(void); { /* 32 kHz */ /* 1/3 1/3 , SEG21:SEG24 */ LCDCRB = (1<Note:
1.
208
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ATmega169V/L
LCD / LCD (LCDDR0 LCDDR1...) LCD (LCDBL) (LCDAB) (LCDCCR) LCD LCD LCD COM1 SEG10 COM0 SEG4 r20 r21 (1)
LCD_update: ; LCD ; sts sts ret LCDDR0, r20 LCDDR6, r21
C (1)
Void LCD_update(unsigned char data1, data2); { /* LCD */ /* */ LCDDR0 = data1; LCDDR6 = data2; }
Note:
1.
LCD
LCD MCU LCD LCD LCD LCD
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(1)
LCD_disable: ; Wait_1: lds r16, LCDCRA sbrs r16, LCDIF rjmp Wait_1 ; 1 LCD ; ldi sts r16, (1<; LCD Wait_2: lds r16, LCDCRA sbrs r16, LCDIF rjmp Wait_2 ; LCD ldi sts ret r16, (0<C (1)
Void LCD_disable(void); { /* */ while ( !(LCDCRA & (1<Note:
1.
210
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ATmega169V/L
LCD A-- LCDCRA
/ 7 LCDEN R/W 0 6 LCDAB R/W 0 5 - R 0 4 LCDIF R/W 0 3 LCDIE R/W 0 2 - R 0 1 - R 0 0 LCDBL R/W 0 LCDCRA
* 7 - LCDEN: LCD LCDENLCD/ LCD LCD / LCD LCD / LCD * 6- LCDAB: LCD LCDAB 0 LCD LCDAB LCD * 5- Res: ATmega169 0 * 4 - LCDIF: LCD LCDIF LCDIE SREG I LCD SOF( ) LCDIF LCDIF 1 LCDIF LCDCRA - - * 3- LCDIE: LCD LCDIE SREG I LCD SOF * 2:1 - Res: ATmega169 0 * 0 - LCDBL: LCD LCDBL
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LCD B-- LCDCRB
/ I
7
LCDCS
6
LCD2B
5
LCDMUX1
4
LCDMUX0
3
-
2
LCDPM2
1
LCDPM1
0
LCDPM0 LCDCRB
R/W 0
R/W 0
R/W 0
R/W 0
R 0
R/W 0
R/W 0
R/W 0
* 7 - LCDCS: LCD LCDCS0LCD LCD ASSR EXCLK / P131 " / " * 6 - LCD2B: LCD 1/2 LCD2B0LCD1/3 LCD1/2 LCD * 5:4 - LCDMUX1:0: LCD Mux LCDMUX1:0 LCD LCD Table 94 Table 94. LCD
LCDMUX1 0 0 1 1 Note: LCDMUX0 0 1 0 1 1/2 1/3 1/4 1/2 or 1/3
(1)
COM COM0 COM0:1 COM0:2 COM0:3
I/O COM1:3 COM2:3 COM3
1/2 or 1/3(1) 1/2 or 1/3
(1)
1. LCD2B 1 1/2 1/3
* 3 - Res: ATmega169
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* 2:0 - LCDPM2:0: LCD LCDPM2:0 Table 95 Table 95. LCD
LCDPM2 0 0 0 0 1 1 1 1 LCDPM1 0 0 1 1 0 0 1 1 LCDPM0 0 1 0 1 0 1 0 1 I/O SEG0:12 SEG0:14 SEG0:16 SEG0:18 SEG0:20 SEG0:22 SEG0:23 SEG0:24 13 15 17 19 21 23 24 25
LCD --LCDFRR
t /
7
-
6
LCDPS2
5
LCDPS1
4
LCDPS0
3
-
2
LCDCD2
1
LCDCD1
0
LCDCD0 LCDFRR
R 0
R/W 0
R/W 0
R/W 0
R 0
R/W 0
R/W 0
R/W 0
* 7 - Res: ATmega169 * 6:4 - LCDPS2:0: LCD LCDPS2:0 (LCDCD2:0) Table 96 LCD (clkLCD_PS) LCD Table 96. LCD
LCDPS2 0 0 0 0 1 1 1 1 LCDPS1 0 0 1 1 0 0 1 1 LCDPS0 0 1 0 1 0 1 0 1 clkLCD/N clkLCD/16 clkLCD/64 clkLCD/128 clkLCD/256 clkLCD/512 clkLCD/1024 clkLCD/2048 clkLCD/4096 LCDCD2:0 = 0, = 1/4, = 64 Hz LCD 8.1 kHz 33 kHz 66 kHz 130 kHz 260 kHz 520 kHz 1 MHz 2 MHz
* 3 - Res: ATmega169
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* 2:0 - LCDCD2:0: LCD LCDCD2:0 Table 97 Table 97. LCD
LCDCD2 0 0 0 0 1 1 1 1 LCDCD1 0 0 1 1 0 0 1 1 LCDCD0 0 1 0 1 0 1 0 1 1 2 3 4 5 6 7 8 ckLCD = 32.768 kHz, N = 16, = 1/4, 256 Hz 128 Hz 85.3 Hz 64 Hz 51.2 Hz 42.7 Hz 36.6 Hz 32 Hz
f clk LCD f frame = ---------------------------------------------------------( K N ( 1 + LCDCD ) ) N = (16 64 128 256 512 1024 2048 4096) K = 8 1/4 1/2 K = 6 1/3 1/3 33% Table 98 Table 98.
cklLCD 4 MHz 4 MHz 32.768 kHz 32.768 kHz 1/4 1/3 Static 1/2 K 8 6 8 8 LCDPS2:0 6 6 0 0 N 2048 2048 16 16 LCDCS2:0 3 3 0 4
4000000/(8*2048*(1+3)) = 61 Hz 4000000/(6*2048*(1+3)) = 81 Hz 32768/(8*16*(1+0)) = 256 Hz 32768/(8*16*(1+4)) = 51 Hz
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LCD -- LCDCCR
/ 7
-
6
-
5
-
4
-
3
LCDCC3
2
LCDCC2
1
LCDCC1
0
LCDCC0 LCDCCR
R 0
R 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
* 7:4 - Res: ATmega169 * 3:0 - LCDCC3:0: LCD LCDCC3:0 VLCDTable 99 Table 99. LCD
LCDCC3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 LCDCC2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 LCDCC1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LCDCC0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 VLDC 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00 3.05 3.10 3.15 3.20 3.25 3.30 3.35
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LCD
LCD 1 ( ) LCD
COM3 COM3 COM3 COM3 COM2 COM2 COM2 COM2 COM1 COM1 COM1 COM1 COM0 COM0 COM0 COM0 /
7 - - SEG323 SEG315 SEG307 - - SEG223 SEG215 SEG207 - - SEG123 SEG115 SEG107 - - SEG023 SEG015 SEG007 R/W 0 6 - - SEG322 SEG314 SEG306 - - SEG222 SEG214 SEG206 - - SEG122 SEG114 SEG106 - - SEG022 SEG014 SEG006 R/W 0 5 - - SEG321 SEG313 SEG305 - - SEG221 SEG213 SEG205 - - SEG121 SEG113 SEG105 - - SEG021 SEG013 SEG005 R/W 0 4 - - SEG320 SEG312 SEG304 - - SEG220 SEG212 SEG204 - - SEG120 SEG112 SEG104 - - SEG020 SEG012 SEG004 R/W 0 3 - - SEG319 SEG311 SEG303 - - SEG219 SEG211 SEG203 - - SEG119 SEG111 SEG103 - - SEG019 SEG011 SEG003 R/W 0 2 - - SEG318 SEG310 SEG302 - - SEG218 SEG210 SEG202 - - SEG118 SEG110 SEG102 - - SEG018 SEG010 SEG002 R/W 0 1 - - SEG317 SEG309 SEG301 - - SEG217 SEG209 SEG201 - - SEG117 SEG109 SEG101 - - SEG017 SEG009 SEG001 R/W 0 0 - SEG324 SEG316 SEG308 SEG300 - SEG224 SEG216 SEG208 SEG200 - SEG124 SEG116 SEG108 SEG100 - SEG024 SEG016 SEG008 SEG000 R/W 0 LCDDR19 LCDDR18 LCDDR17 LCDDR16 LCDDR15 LCDDR14 LCDDR13 LCDDR12 LCDDR11 LCDDR10 LCDDR9 LCDDR8 LCDDR7 LCDDR6 LCDDR5 LCDDR4 LCDDR3 LCDDR2 LCDDR1 LCDDR0
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JTAG
* JTAG (IEEE std. 1149.1 ) * IEEE std. 1149.1 (JTAG) *
- - RAM - - - EEPROM Flash * - AVR - - - - * JTAG Flash EEPROM * AVR Studio(R)
AVR IEEE std. 1149.1 JTAG * * * JTAG PCB
JTAG P274 "JTAG" P224 "IEEE 1149.1 (JTAG)" JTAG ATMEL Figure 104 JTAG TAPTCKTMS TAP JTAG TDI ( ) TDO( ) ( ) JTAG ID JTAG( ) JTAG
--TAP
JTAGAVR JTAG - TAP * * * * TMS: TAP TCK: JTAG TCK TDI: ( ) TDO:
1149.1 TAP TRST - AVR JTAGEN TAP TAP JTAGEN MCUCSR JTD TAP JTAG TAP (TDO) JTAG TAP ( TDI )
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JTAG RESET ( ) RESET Figure 104.
I/O PORT 0
DEVICE BOUNDARY
BOUNDARY SCAN CHAIN
TDI TDO TCK TMS
TAP CONTROLLER
JTAG PROGRAMMING INTERFACE
AVR CPU INSTRUCTION REGISTER ID REGISTER M U X BYPASS REGISTER FLASH MEMORY Address Data INTERNAL SCAN CHAIN PC Instruction
BREAKPOINT UNIT
FLOW CONTROL UNIT DIGITAL PERIPHERAL UNITS ANALOG PERIPHERIAL UNITS Analog inputs
BREAKPOINT SCAN CHAIN ADDRESS DECODER JTAG / AVR CORE COMMUNICATION INTERFACE
OCD STATUS AND CONTROL
Control & Clock lines
I/O PORT n
218
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Figure 105. TAP
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
TAP
TAP 16 JTAG Figure 105 TCK TMS( ) Test-Logic-Reset LSB Run-Test/Idle( - / ) JTAG * TCK TMS 1, 1, 0, 0 - ShiftIR TCK TDI 4 JTAG JTAG 3 LSB TMS Shift-IR MSBTMSShift-IRJTAG TDI IR 0x01 TDO JTAG TDI TDO TMS 1, 1, 0Run-Test/IdleUpdate-IR Exit-IR, Pause-IR, Exit2-IR TCK TMS 1, 0, 0 - Shift-DR TDI TCK ( JTAG
*
*
219
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JTAG ) Shift-DR TMS MSB TMS Shift-IR MSB TDI Capture-DR TDO * TMS 1, 1, 0 Run-Test/Idle Update-DR Exit-IR, Pause-IR, Exit2-IR
JTAG Run-Test/Idle JTAG Run-Test/Idle
Note: TMS TCK TAP Test-Logic-Reset TAP
JTAG P223 " "

P224 "IEEE 1149.1 (JTAG) " Figure 104 * * * AVR CPU CPU JTAG
/ AVR CPU AVR CPU I/O CPU JTAG * * * * * ( ) ( )
AVR Studio JTAG P222 " JTAG " JTAGEN JTAG OCDEN LB1 LB2 AVR Studio AVR AVR AVR AVR Studio(R) Atme AVR C AVR StudioMicrosoft(R) Windows(R) 95/98/2000, Windows NT(R)Windows XP(R) AVR Studio AVR Studio
220
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AVR Studio (Trace) (Step Over) ( BREAK ) ( )
JTAG
PRIVATE0; 0x8 PRIVATE1; 0x9 PRIVATE2; 0xA PRIVATE3; 0xB
JTAG ATMEL ATMEL JTAG JTAG JTAG JTAG
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I/O
--OCDR
t / I 7 MSB/IDRD R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 OCDR
OCDR CPU I/O - IDRD - CPU OCDR 7 LSB OCDR MSB IDRD IDRD AVR I/O OCDEN OCDR MCU OCDR MCU I/O
JTAG
JTAG AVR JTAG --TCK, TMS, TDI TDO() 12V JTAG JTAGEN MCUCR JTD JTAG * * * * Flash EEPROM
LB1 LB2 OCDEN JTAG JTAG P274 " JTAG "
* * IEEE: IEEE Std. 1149.1-1990. IEEE Standard Test Access Port and Boundary-scan Architecture, IEEE, 1993. Colin Maunder: The Board Designers Guide to Testable Logic Circuits, AddisonWesley, 1992.
222
ATmega169V/L
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IEEE 1149.1 (JTAG)
* * * * *
JTAG ( IEEE std. 1149.1 ) JTAG IDCODE AVR AVR_RESET
I/O JTAG IC TDI/TDO TAP IEEE 1149.1 JTAG IDCODE BYPASS SAMPLE/PRELOAD EXTEST AVR JTAG AVR_RESET IDCODE JTAG ID AVR HIGHZ BYPASS RESET AVR_RESET EXTEST EXTEST JTAG IR SAMPLE/PRELOAD EXTEST SAMPLE/PRELOAD TAGEN I/O MCUCR JTD JTAG JTAG JTAG TCK
* * * * (Bypass)
TDI TDO Capture-DR 0 Figure 106 Figure 106.
MSB
ID LSB
31
4
28
27
16
12
11
ID 11
1
1
0
1
223
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Table 100 Table 100. JTAG
ATmega169 A ATmega169 B ATmega169 C ATmega169 D JTAG (Hex) 0x0 0x1 0x2 0x3
16 Table 101 ATmega169 JTAG Table 101. AVR JTAG
ATmega169 JTAG (Hex) 0x9405
ID
ID 11 Table 102 ATMEL JTAG ID Table 102. ID
ATMEL JTAG ID (Hex) 0x01F
224
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
AVR JTAG HIGHZ ( P24 " " ) Figure 107 Figure 107.
To TDO
From Other Internal and External Reset Sources From TDI Internal reset
D
Q
ClockDR * AVR_RESET
I/O P228 " "
JTAG
4 16 JTAG AVR HIGHZ AVR_RESET LSB OPCODE hex TDI TDO
225
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EXTEST; 0x0
EXTEST JTAG AVR JTAG IR EXTEST * * * Capture-DR Shift-DR TCK Update-DR
IDCODE; 0x1
IDCODEJTAG 32ID ID JEDEC IDCODE * * Capture-DR IDCODE Shift-DR TCK IDCODE
SAMPLE_PRELOAD; 0x2
SAMPLE_PRELOADJTAG / * * * Capture-DR Shift-DR TCK Update-DR
AVR_RESET; 0xC
AVR_RESETAVRJTAG AVRJTAG TAP 1 * Shift-DR TCK
BYPASS; 0xF
BYPASS JTAG * * Capture-DR 0 Shift-DRTDI TDO
I/O
MCU --MCUCR MCU MCU .
/ 7 JTD R/W 0 6 - R 0 5 - R 0 4 PUD R/W 0 3 - R 0 2 - R 0 1 IVSEL R/W 0 0 IVCE R/W 0 MCUCR
* 7 - JTD: JTAG 0 JTAGEN JTAG 1 JTAG JTAG JTD 226
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ATmega169V/L
JTD JTAG JTAG JTD JTAG TDO MCU --MCUSR MCU MCU
/ I 7 - R 0 6 - R 0 5 - R 0 4 JTRF R/W 3 WDRF R/W 2 BORF R/W 1 EXTRF R/W 0 PORF R/W MCUSR
* 4 - JTRF: JTAG JTAG AVR_RESET JTAG 1 JTRF 0 JTRF
I/O Figure 108 - PUExn - - OCxn - ODxn - IDxn Figure 109 P50 "I/O " Figure 109 Figure 108 - ID - PINxn ( ID ) PORT - DD - PUExn - PUD * DDxn * PORTxn Figure 109
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Figure 108. .
ShiftDR To Next Cell EXTEST Vcc
Pullup Enable (PUE) FF2 0 D 1 G Q D Q LD2
0 1
Output Control (OC) FF1 0 D 1 G Q D Q LD1 0 1
Output Data (OD) Port Pin (PXn)
0 1 0
FF0 D 1 Q
LD0 D G Q
0 1
Input Data (ID)
From Last Cell
ClockDR
UpdateDR
228
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ATmega169V/L
Figure 109.
See Boundary-scan Description for Details!
PUExn
PUD
Q
D
DDxn
Q CLR
OCxn
RESET
WDx
RDx
Pxn 1
Q D
IDxn
ODxn
PORTxn Q CLR
0
RESET SLEEP RRx
WPx WRx
SYNCHRONIZER
D Q D Q
RPx
PINxn
L
Q
Q
CLK I/O
PUD: PUExn: OCxn: ODxn: IDxn: SLEEP:
PULLUP DISABLE PULLUP ENABLE for pin Pxn OUTPUT CONTROL for pin Pxn OUTPUT DATA to pin Pxn INPUT DATA from pin Pxn SLEEP CONTROL
WDx: RDx: WRx: RRx: RPx: WPx: CLK I/O :
WRITE DDRx READ DDRx WRITE PORTx READ PORTx REGISTER READ PORTx PIN WRITE PINx REGISTER I/O CLOCK
RESET 5V 12V Figure 110 5V RSTT 12V RSTHV Figure 110. l
To Next Cell
ShiftDR
From System Pin
To System Logic
FF1
0 D 1 Q
From Previous Cell
ClockDR
AVR RC ) (
DATA BUS
229
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Figure 111 / RC Figure 111.
XTAL1/TOSC1 XTAL2/TOSC2
ShiftDR
To Next Cell
EXTEST
Oscillator
ENABLE OUTPUT
ShiftDR
To Next Cell
From Digital Logic
0 1 0 D 1 G Q D Q 0 D 1 Q
To System Logic
FF1
From Previous Cell
ClockDR
UpdateDR From Previous Cell ClockDR
Table 103 XTAL1 XTAL1/XTAL2 Table 103. (1)(2)(3)
EXTCLKEN OSCON OSC32EN Notes: EXTCLK (XTAL1) OSCCK OSC32CK 0 1 1
1. 2. JTAG TCK 3.
230
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ATmega169V/L
Figure 112 Figure 113 Table 104 Figure 112.
BANDGAP REFERENCE ACBG ACD
ACO
AC_IDLE
ACME ADCEN ADC MULTIPLEXER OUTPUT
Figure 113. ADC
ShiftDR To Next Cell EXTEST
From Digital Logic/ From Analog Ciruitry 0 D 1 G Q D Q
0 1
To Analog Circuitry/ To Digital Logic
From Previous Cell
ClockDR
UpdateDR
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Table 104.
AC_IDLE ACO 1 C 0 0 C 0
ACME ACBG

ADC mux
C C
ADC
Figure 114ADC Figure 110 ADC Figure 114. AD
VCCREN
AREF
IREFEN
To Comparator
1.11V ref
MUXEN_7 ADC_7 MUXEN_6 ADC_6 MUXEN_5 ADC_5 MUXEN_4 ADC_4
PASSEN
SCTEST
ADCBGEN
EXTCH MUXEN_3 ADC_3 MUXEN_2 ADC_2 MUXEN_1 ADC_1 MUXEN_0 ADC_0 NEGSEL_2
ADC_2
1.22V ref
PRECH
PRECH AREF
AREF
DACOUT
DAC_9..0
10-bit DAC + COMP -
COMP
ADCEN
+
ACTEN
1x
-
HOLD GNDEN
NEGSEL_1
ADC_1
NEGSEL_0
ADC_0
ST ACLK AMPEN
Table 105
232
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ATmega169V/L
Table 105. ADC(1)
ADC 0 0 CPUADC 0 0
COMP ACLK
ADC DAC 9 DAC 8 DAC 7 DAC 6 DAC 5 DAC 4 DAC 3 DAC 2 DAC 1 DAC 0 ADC 0 - 3 ACLK DAC AREF 7 6 5 4 3 2 1
ACTEN ADCBGEN ADCEN AMPEN DAC_9 DAC_8 DAC_7 DAC_6 DAC_5 DAC_4 DAC_3 DAC_2 DAC_1 DAC_0 EXTCH GNDEN HOLD

0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1
0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1
IREFEN MUXEN_7 MUXEN_6 MUXEN_5 MUXEN_4 MUXEN_3 MUXEN_2 MUXEN_1

0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
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Table 105. ADC(1) (Continued)
ADC 1 0 0 0 1 1 0 CPUADC 1 0 0 0 1 1 0
MUXEN_0 NEGSEL_2 NEGSEL_1 NEGSEL_0 PASSEN PRECH SCTEST
0 2 1 0 ( ) TEST x10 ADC_4 AMPEN ACLK Vcc
ST
0
0
VCCREN Note:
0
0
1. Figure 114 Figure 114 S&H ADC
ADC Table 105 AVR ADC Figure 114 DAC[9:0] DAC[9:0] ADC ADC * * ADC ADC ( 10 ) ADC / ADC 200ns HOLD ( ) DAC 0x200
*
5.0V AREF VCC ADC 3 1.5V 5%
The lower limit is: The upper limit is: 1024 1,5V 0,95 5V = 291 = 0x123 1024 1,5V 1,05 5V = 323 = 0x143
Table 106 Table 105 Table 106 DAC " " 234
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ATmega169V/L
JTAG Table 106. ADC
PA3. Pullup_ Enable
1 2 3 4 5 6 7 8 9 10 11
SAMPLE_ PRELOAD EXTEST
ADCEN
DAC
MUXEN
HOLD
PRECH
PA3. Data
PA3. Control
1 1 1 1 1
0x200 0x200 0x200 0x123 0x123 0x200 0x200 0x200 0x143 0x143 0x200
0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08 0x08
1 0 1 1 1 1 0 1 1 1 1
1 1 1 1 0 1 1 1 1 0 1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
COMP 0
1 1 1 1 1
COMP 1
1
HOLD TCK 5 HOLD TCK thold,max 5
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Table 107TDITDO 0LSB A Figure 108 PXn. Data FF0PXn. Control FF1PXn. Pull-up_enable FF2 C2 45 3 JTAGTAP Table 107. ATmega169
197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 AC_IDLE ACO ACME AINBG COMP ACLK ACTEN PRIVATE_SIGNAL1(1) ADCBGEN ADCEN AMPEN DAC_9 DAC_8 DAC_7 DAC_6 DAC_5 DAC_4 DAC_3 DAC_2 DAC_1 DAC_0 EXTCH GNDEN HOLD IREFEN MUXEN_7 MUXEN_6 MUXEN_5 MUXEN_4 ADC
236
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Table 107. ATmega169 (Continued)
168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 MUXEN_3 MUXEN_2 MUXEN_1 MUXEN_0 NEGSEL_2 NEGSEL_1 NEGSEL_0 PASSEN PRECH ST VCCREN PE0.Data PE0.Control PE0.Pull-up_Enable PE1.Data PE1.Control PE1.Pull-up_Enable PE2.Data PE2.Control PE2.Pull-up_Enable PE3.Data PE3.Control PE3.Pull-up_Enable PE4.Data PE4.Control PE4.Pull-up_Enable PE5.Data PE5.Control PE5.Pull-up_Enable PE6.Data PE6.Control PE6.Pull-up_Enable PE7.Data PE7.Control PE7.Pull-up_Enable PB0.Data B E ADC
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Table 107. ATmega169 (Continued)
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 PB0.Control PB0.Pull-up_Enable PB1.Data PB1.Control PB1.Pull-up_Enable PB2.Data PB2.Control PB2.Pull-up_Enable PB3.Data PB3.Control PB3.Pull-up_Enable PB4.Data PB4.Control PB4.Pull-up_Enable PB5.Data PB5.Control PB5.Pull-up_Enable PB6.Data PB6.Control PB6.Pull-up_Enable PB7.Data PB7.Control PB7.Pull-up_Enable PG3.Data PG3.Control PG3.Pull-up_Enable PG4.Data PG4.Control PG4.Pull-up_Enable PG5 RSTT RSTHV EXTCLKEN OSCON RCOSCEN OSC32EN ( ) ( ) / G B
238
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Table 107. ATmega169 (Continued)
96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 EXTCLK (XTAL1) OSCCK RCCK OSC32CK PD0.Data PD0.Control PD0.Pull-up_Enable PD1.Data PD1.Control PD1.Pull-up_Enable PD2.Data PD2.Control PD2.Pull-up_Enable PD3.Data PD3.Control PD3.Pull-up_Enable PD4.Data PD4.Control PD4.Pull-up_Enable PD5.Data PD5.Control PD5.Pull-up_Enable PD6.Data PD6.Control PD6.Pull-up_Enable PD7.Data PD7.Control PD7.Pull-up_Enable PG0.Data PG0.Control PG0.Pull-up_Enable PG1.Data PG1.Control PG1.Pull-up_Enable PC0.Data PC0.Control C G D ( )
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Table 107. ATmega169 (Continued)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 PC0.Pull-up_Enable PC1.Data PC1.Control PC1.Pull-up_Enable PC2.Data PC2.Control PC2.Pull-up_Enable PC3.Data PC3.Control PC3.Pull-up_Enable PC4.Data PC4.Control PC4.Pull-up_Enable PC5.Data PC5.Control PC5.Pull-up_Enable PC6.Data PC6.Control PC6.Pull-up_Enable PC7.Data PC7.Control PC7.Pull-up_Enable PG2.Data PG2.Control PG2.Pull-up_Enable PA7.Data PA7.Control PA7.Pull-up_Enable PA6.Data PA6.Control PA6.Pull-up_Enable PA5.Data PA5.Control PA5.Pull-up_Enable PA4.Data PA4.Control A G C
240
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ATmega169V/L
Table 107. ATmega169 (Continued)
24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note: PA4.Pull-up_Enable PA3.Data PA3.Control PA3.Pull-up_Enable PA2.Data PA2.Control PA2.Pull-up_Enable PA1.Data PA1.Control PA1.Pull-up_Enable PA0.Data PA0.Control PA0.Pull-up_Enable PF3.Data PF3.Control PF3.Pull-up_Enable PF2.Data PF2.Control PF2.Pull-up_Enable PF1.Data PF1.Control PF1.Pull-up_Enable PF0.Data PF0.Control PF0.Pull-up_Enable 1. PRIVATE_SIGNAL1 0 F A
(BSDL)
241
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Boot Loader -- RWW
Boot Loader MCU - (ReadWhile-Write RWW) MCU Flash Boot Loader Boot Loader ( ) Boot Loader Boot Loader Boot Loader Boot Loader Boot Loader Boot Loader * * * * * * *
RWW Boot Loader ( Boot ) Flash (1) RWW 1. ( P260 Table 125 )
Boot Loader
Note:
Boot Loader Flash
Flash Boot Loader ( Figure 116) BOOTSZ P253 Table 113 Figure 116 Boot (Boot 0) P245 Table 109 SPM Boot Loader Boot Loader BLS BLS SPM SPM BLS Boot Loader Boot Loader (Boot 1) P245 Table 110 CPU RWW CPU Boot Loader BOOTSZ ---- - (RWW) - (NRWW) RWW- NRWW P253 Table 114 P244 Figure 116 * * RWW NRWW NRWW CPU
BLS--Boot Loader
RWW RWW Flash
Boot Loader RWW "RWW " ( ) Boot Loader RWW---- Boot Loader RWW NRWW Flash RWW RWW ( call/jmp/lpm ) Boot Loader Boot Loader NRWW RWW (SPMCSR) RWW RWWSB RWW RWWSB RWWSB P246 " - SPMCSR"
242
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NRWW---- Boot Loader RWW NRWW Boot Loader NRWW CPU Table 108. RWW
Z ? RWW NRWW ? NRWW CPU ? RWW ?
Figure 115. RWW NRWW
Read-While-Write (RWW) Section
Z-pointer Addresses RWW Section
Z-pointer Addresses NRWW Section
No Read-While-Write (NRWW) Section
CPU is Halted During the Operation Code Located in NRWW Section Can be Read During the Operation
243
2514I-AVR-10/03
Figure 116.
Program Memory BOOTSZ = '11' 0x0000
Read-While-Write Section Read-While-Write Section
Program Memory BOOTSZ = '10' 0x0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend Program Memory BOOTSZ = '00'
Boot Loader Flash Section
End Application Start Boot Loader Flashend
Program Memory BOOTSZ = '01' 0x0000
Read-While-Write Section Read-While-Write Section
0x0000
Application Flash Section
Application Flash Section
No Read-While-Write Section
End RWW Start NRWW Application Flash Section End Application Start Boot Loader Boot Loader Flash Section Flashend
No Read-While-Write Section
End RWW, End Application Start NRWW, Start Boot Loader
Boot Loader Flash Section
Flashend
Note:
1. P253 Table 113
Boot Loader Boot Loader Boot * * * * Flash MCU MCU Boot Loader Flash MCU Flash MCU
Table 109 Table 110Boot ( 2) SPM / ( 1) LPM/SPM /
244
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Table 109. Boot
BLB0 1 2 3
0 ( )(1)
BLB01 1 0 0 SPM/LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader 1 1 0
BLB02
4
0
1
Note:
1. "1" "0"
Table 110. Boot
BLB1 1 2 3 BLB12 1 1 0
1 (Boot Loader )(1)
SPM/LPM Boot Loader SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader Boot Loader 1 0 0
BLB11
4
0
1
Note:
1. "1" "0"
Boot Loader
Boot Loader USART SPI Boot Boot Boot Loader MCU Boot Boot Table 111. Boot (1)
BOOTRST 1 0 Note: = ( 0x0000) =Boot Loader ( P253 Table 113 )
1. "1" , "0"
--SPMCSR
Boot Loader
/ 7
SPMIE
6
RWWSB
5
-
4
RWWSRE
3
BLBSET
2
PGWRT
1
PGERS
0
SPMEN SPMCSR
R/W 0
R 0
R 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
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* 7 - SPMIE: SPM SPMIE I SPM SPMCSR SPMEN SPM * 6 - RWWSB:RWW RWW ( ) RWWSB 1 RWWSB RWW RWWSRE 1 RWWSB RWWSB * 5 - Res: ATmega169 0 * 4 - RWWSRE: RWW RWW() RWW(RWWSB1) (SPMEN)RWW RWWSRE SPMEN 1 SPM RWW (SPMEN ),RWW RWWSRE * 3 - BLBSET: Boot SPMEN SPM R0 Boot R1 Z SPM BLBSET SPMCSR BLBSET SPMEN LPM ( Z Z0) P251 " " * 2 - PGWRT: SPMEN SPM Flash Z R1 R0 SPM PGWRT NRWW CPU * 1 - PGERS: SPMEN SPM Z R1 R0 SPM PGERS NRWW CPU * 0 - SPMEN: SPM RWWSRE BLBSET PGWRT PGERS SPM SPMEN SPM R1:R0 Z LSB Z SPM SPM SPMEN SPMEN 1 "10001", "01001", "00101", "00011" "00001"
246
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Z SPM
ZH (R31) ZL (R30) 15 Z15 Z7 7 14 Z14 Z6 6 13 Z13 Z5 5 12 Z12 Z4 4 11 Z11 Z3 3 10 Z10 Z2 2 9 Z9 Z1 1 8 Z8 Z0 0
Flash (P260 Table 125 ) Figure 117 Boot Loader Z Z SPM Boot Loader Z LPM Z Z ( Z0) Figure 117. SPM(1)
BIT Z - REGISTER PCMSB PROGRAM COUNTER
PCPAGE
15
ZPCMSB
ZPAGEMSB
10 0
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. Figure 117 P254 Table 115 2. PCPAGE PCWORD P260 Table 125
SPM 1 * * * * 247
2
2514I-AVR-10/03
* *

( ) Flash 1 Boot Loader - - Flash 2 P253 " Boot Loader "
248
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ATmega169V/L
SPM Z "X0000011" SPMCSR SPM R1 R0 Z PCPAGE Z * * ( ) RWW NRWW NRWW CPU
Z R1:R0 "00000001" SPMCSR SPM Z PCWORD SPMCSR RWWSRE SPM EEPROM
Z "X0000101" SPMCSR SPMR1 R0 Z PCPAGE Z * * RWW NRWW NRWW CPU
SPM
SPM SPMCSR SPMEN SPMCSR SPM BLS RWW P45 " " Boot 11 Boot Loader Boot Loader Boot Loader Boot Loader Boot 11 Boot Loader ( ) RWW RWW SPMCSR RWWSB P45 " " BLS RWW RWWSRE 1 RWWSB P253 " Boot Loader "
BLS
RWW
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SPM Boot Loader
Boot Loader R0 "X0001001"SPMCSR SPM Boot Loader MCU Boot Loader .
R0 7 1 6 1 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 1 0 1
Boot Loader Flash Table 109 Table 110 R0 5..2 0 SPMCSR BLBSET SPMEN SPM Boot Z Z 0x0001( lOck ) R0 7, 6, 1, 0 1 EEPROM SPMCSR EEPROM SPMCSR EECR EEWE 0x0001 Z SPMCSRBLBSET SPMEN SPMCSRCPU LPM CPU LPM CPU SPM BLBSET SPMEN BLBSET SPMEN LPM
Rd 7 - 6 - 5 BLB12 4 BLB11 3 BLB02 2 BLB01 1 LB2 0 LB1
0x0000ZSPMCSRBLBSET SPMEN SPMCSR CPU LPM (FLB) P257 Table 120
Rd 7 FLB7 6 FLB6 5 FLB5 4 FLB4 3 FLB3 2 FLB2 1 FLB1 0 FLB0
0x0003 Z SPMCSR BLBSET SPMEN SPMCSR CPU LPM (FHB) P257 Table 119
Rd 7 FHB7 6 FHB6 5 FHB5 4 FHB4 3 FHB3 2 FHB2 1 FHB1 0 FHB0
When reading the Extended Fuse byte, load in the Z-pointer. When an LPM instruction is executed within three cycles after the BLBSET and SPMEN bits are set in the SPMCSR, the value of the Extended Fuse byte (EFB) will be loaded in the destination register as shown below. Refer to P256 Table 118 for detailed description and mapping of the Extended Fuse byte 0x0002 Z SPMCSR BLBSET SPMEN SPMCSR CPU LPM (EFB) P256 Table 118
Rd 7 - 6 - 5 - 4 - 3 EFB3 2 EFB2 1 EFB1 0 EFB0
0 1 250
ATmega169V/L
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ATmega169V/L
VCC CPU CPU ( ) 1. Boot Loader Boot Loader Boot Loader 2. AVR RESET BOD 3. AVR CPU SPMCSR SPM RC Table 112 CPU Table 112. SPM
( SPM ) 3.7 ms 4.5 ms
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Boot Loader
;- RAM ;Y RAM ;Z ;- ;- Boot ( Do_spm ) ; ( ) NRWW ;- r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; ; ;- Boot loader , .equ PAGESIZEB = PAGESIZE*2 ;PAGESIZEB .org SMALLBOOTSTART Write_page: ; ldi spmcrval, (1<; ;PAGESIZEB<=256
;PAGESIZEB<=256 subi
; subi ZL, low(PAGESIZEB) ; sbci ZH, high(PAGESIZEB) ;PAGESIZEB<=256 ldi spmcrval, (1<; ;PAGESIZEB<=256 ;
;PAGESIZEB<=256 subi
; RWW ; RWW Return: in temp1, SPMCSR sbrs temp1, RWWSB ; RWWSB 1 RWW ret ; RWW
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ldi spmcrval, (1<ATmega169 Boot Loader
In Table 113 through Table 115, the parameters used in the description of the Self-Programming are give Table 113 Table 115 Table 113. Boot (1)
BOOT SZ1 1 1 0 0 BOOTS Z0 1 0 1 0 Boot 128 256 512 1024 0x0000 0x1F7F 0x0000 0x1EFF 0x0000 0x1DFF 0x0000 0x1BFF Boot Loader 0x1F80 0x1FFF 0x1F00 0x1FFF 0x1E00 0x1FFF 0x1C00 0x1FFF 0x1F7F 0x1EFF 0x1DFF 0x1BFF Boot (Boot Loader ) 0x1F80 0x1F00 0x1E00 0x1C00
2 4 8 16
Note:
1. BOOTSZ Figure 116
Table 114. RWW (1)
Flash - (RWW) - (NRWW) Note: 112 16 0x0000 - 0x1BFF 0x1C00 - 0x1FFF
1. P244 "NRWW -- - " P243 "RWW -- - "
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Table 115. Figure 117 Z (1)
PCMSB PAGEMSB ZPCMSB ZPAGEMS B PCPAGE PCWORD Note: PC[12:6] PC[5:0] 12 5 Z13 Z6 Z13:Z7 Z6:Z1 Z ( 13 PC[12:0]) ( 64 6 PC [5:0]) Z PCMSB Z0 ZPCMSB PCMSB + 1 Z PAGEMSB Z0 ZPAGEMSB PAGEMSB + 1 ( 0)
1. Z15:Z14: Z0: SPM 0 LPM Z P248 " "
254
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ATmega169 6 ("0") ("1") Table 117 "1"
Table 116. (1)
7 6 BLB12 BLB11 BLB02 BLB01 LB2 LB1 Note: 5 4 3 2 1 0 - - Boot Boot Boot Boot 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( ) 1 ( )
1. "1" "0"
Table 117. (1)(2)
LB 1 2 3 BLB0 1 2 LB2 1 1 0 BLB02 1 1 LB1 1 0 0 BLB01 1 0 SPM LPM SPM SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader SPM/LPM Boot Loader EEPROM (1) EEPROM (1)
3
0
0
4 BLB1 1
0 BLB12 1
1 BLB11 1
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Table 117. (1)(2) (Continued) (Continued)
2 1 0 SPM Boot Loader SPM Boot Loader LPM Boot Loader Boot Loader LPM Boot Loader
3
0
0
4 Notes:
0
1
1. LB1 LB2 Boot 2. "1" , "0"
ATmega169 Table 118 Table 120 0 Table 118.
- - - - BODLEVEL2 BODLEVEL1 BODLEVEL0 Notes:
(1) (1) (1)
7 6 5 4 3 2 1
- - - - BOD BOD BOD
1 1 1 1 1 ( ) 1 ( ) 1 ( )
1. BODLEVEL P39 Table 17
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Table 119.
OCDEN
(4) (5)
7 6 5 4 3 2 1 0
OCD JTAG EEPROM Boot ( Table 121) Boot ( Table 121)
1 ( OCD ) 0 ( JTAG ) 0 ( SPI ) 1 ( ) 1 (, EEPROM ) 0 ( )(2) 0 ( )(2) 1 ( )
JTAGEN SPIEN(1) WDTON
(3)
EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Note:
1. SPIEN 2. BOOTSZ1..0 Boot P259 Table 121 3. P42 " - WDTCR" 4. OCDEN JTAGEN OCDEN 5. JTAG JTAGEN JTAG TDO
Table 120.
CKDIV8(4) CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Note:
(3)
7 6 5 4 3 2 1 0
8
0 ( ) 1 ( ) 1 ( )(1) 0 ( )(1) 0 ( )(2) 0 ( )(2) 1 ( )(2) 0 ( )(2)
1. SUT1..0 P37 Table 16 2. CKSEL3..0RC8 MHz P26 Table 6 3. CKOUT PORTE7 P29 " " 4. P30 " "
1(LB1)
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EESAVE Atmel ATmega169 1. 0x000: 0x1E ( Atmel ) 2. 0x001: 0x94 ( 16K ) 3. 0x002: 0x05 ( 0x001 0x94 ATmega169)
ATmega169 RC 0x000 OSCCAL RC
ATmega169 EEPROM 250 ns
ATmega169 Figure 118Table 121 XA1/XA0 XTAL1 Table 123 WR OE Table 124 Figure 118.
+5V RDY/BSY OE WR BS1 XA0 XA1 PAGEL +12 V BS2 PD1 PD2 PD3 PD4 PD5 PD6 PD7 RESET PA0 XTAL1 GND
PB7 - PB0
VCC +5V AVCC DATA
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Table 121.
RDY/BSY OE WR BS1 XA0 XA1 PAGEL BS2 DATA PD1 PD2 PD3 PD4 PD5 PD6 PD7 PA0 PB7-0 I/O O I I I I I I I I/O 0: , 1: ( ). ( ). 1("0" , "1" ). XTAL 0 XTAL 1 EEPROM 2("0" , "1" ) (OE )
Table 122.
PAGEL XA1 XA0 BS1 Prog_enable[3] Prog_enable[2] Prog_enable[1] Prog_enable[0] 0 0 0 0
Table 123. XA1 XA0
XA1 0 0 1 1 XA0 0 1 0 1 XTAL1 EEPROM ( BS1 ) ( BS1 )
259
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Table 124.
1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 Flash EEPROM Flash EEPROM
Table 125.
8K (16K ) 64 PCWORD PC[5:0] 128 PCPAGE PC[12:6] PCMSB 12
Table 126. EEPROM
EEPROM 512 4 PCWORD EEA[1:0] 128 PCPAGE EEA[8:2] EEAMSB 8
Table 127.
MOSI MISO SCK PB2 PB3 PB1 I/O I O I t
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1. VCC GND 4.5 - 5.5V 2. RESET XTAL1 6 3. P259 Table 122 Prog_enable "0000" 100 ns 4. RESET 11.5 - 12.5V RESET +12V 100 ns Prog_enable 5. 50 s * * * 0xFF Flash EEPROM( EESAVE ) Flash EEPROM 256
Flash EEPROM(1) Flash / EEPROM
Note: 1. EESAVE EEPRPOM
" " 1. XA1 XA0 10 2. BS1 0 3. DATA "1000 0000" 4. XTAL1 5. WR RDY/BSY 6. RDY/BSY Flash Flash P260 Table 125 Flash Flash A " Flash" 1. XA1 XA0 "10" 2. BS1 0 3. DATA "0001 0000" Flash 4. XTAL1 B 1. XA1 XA0 "00" 2. BS1 0 3. DATA (0x00 - 0xFF) 4. XTAL1 C 1. XA1 XA0 "01" 2. DATA (0x00 - 0xFF)
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3. XTAL1 D 1. BS1 1 2. XA1 XA0 "01" 3. DATA (0x00 - 0xFF) 4. XTAL1 E 1. BS1 1 2. PAGEL ( Figure 120 ) F B E FLASH P263 Figure 119 8 ( < 256) G 1. XA1 XA0 00 2. BS1 1 3. DATA (0x00 - 0xFF) 4. XTAL1 H 1. WR RDY/BSY 2. RDY/BSY ( Figure 120 ) I B H Flash J 1. 1. XA1 XA0 10 2. DATA " 0000 0000" 3. XTAL1
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Figure 119. Flash (1)
PCMSB PROGRAM COUNTER
PCPAGE
PAGEMSB
PCWORD
PAGE ADDRESS WITHIN THE FLASH PROGRAM MEMORY
PAGE
WORD ADDRESS WITHIN A PAGE
PAGE INSTRUCTION WORD PCWORD[PAGEMSB:0]: 00 01 02
PAGEEND
Note:
1. PCPAGE PCWORD P260 Table 125
Figure 120. Flash (1)
F
A
DATA 0x10
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
B
ADDR. LOW
C
DATA LOW
D
DATA HIGH
E
XX
G
ADDR. HIGH
H
XX
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
1. " XX" Flash
EEPROM
Table 126 on page 271 EEPROM EEPROM EEPROM ( P262 " Flash " ) 1. A "0001 0001" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. C (0x00 - 0xFF) 5. E ( PAGEL ) K 3 5 L EEPROM 263
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1. BS 0 2. WR EEPROM RDY/BSY 3. RDY/BSY ( Figure 121) Figure 121. EEPROM
K
A
DATA 0x11
G
ADDR. HIGH
B
ADDR. LOW
C
DATA
E
XX
B
ADDR. LOW
C
DATA
E
XX
L
XA1
XA0
BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Flash
Flash ( P262 " Flash " ) 1. A "0000 0010" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE 1 BS1 0 DATA Flash 5. BS 1 DATA Flash OE 1
EEPROM
( P262 " Flash " ) 1. A "0000 0011" 2. G (0x00 - 0xFF) 3. B (0x00 - 0xFF) 4. OE 0 BS1 0 DATA EEPROM 5. OE 1
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( P262 " Flash " ) 1. A "0100 0000" 2. C: 0 3. WR RDY/BSY ( P262 " Flash " ) 1. A "0100 0000" 2. C 0 3. BS1 1 BS2 0 4. WR RDY/BSY 5. BS1 0 ( P262 " Flash " ) 1. 1. A "0100 0000" 2. 2. C 0 3. 3. BS1 1 BS2 1 4. 4. WR RDY/BSY 5. 5. BS2 0 Figure 122.
Write Fuse Low byte A
DATA
0x40
Write Fuse high byte A C
DATA XX
Write Extended Fuse byte A
0x40
C
DATA XX
C
DATA XX
0x40
XA1
XA0
BS1
BS2
XTAL1
WR
RDY/BSY
RESET +12V
OE
PAGEL
( P262 " Flash " ) 1. A "0010 0000" 2. C. n 0 LB 3(LB1 LB2 ) 3. WR RDY/BSY
( P262 " Flash " ) 1. A "0000 0100" 2. OE BS2 BS1 0 DATA (0 ) 3. OE 0 BS2 BS1 1 DATA (0 ) 265
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4. OE BS1 0 BS2 1 DATA (0 ) 5. OE BS2 0 BS1 1 DATA (0 ) 6. OE 1 Figure 123. BS1 BS2
Fuse Low Byte 0
0 Extended Fuse Byte BS2 Lock Bits 0 1 1 DATA
Fuse High Byte BS2
1
BS1
( P262 " Flash " ) 1. A "0000 1000" 2. B 0x00 - 0x02 3. OE 0 BS1 1 DATA 4. OE 1
( P262 " Flash " ) 1. A "0000 1000" 2. B 0x00 3. OE 0 BS1 1 DATA 4. OE 1
Figure 124.
tXLWL XTAL1 tDVXH Data & Contol (DATA, XA0/1, BS1, BS2) tBVPH PAGEL WR RDY/BSY tWLRH tPHPL tWLWH tPLWL
WLRL
tXHXL tXLDX
tPLBX t BVWL
tWLBX
266
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Figure 125. (1)
LOAD ADDRESS (LOW BYTE) LOAD DATA (LOW BYTE)
t XLXH
LOAD DATA LOAD DATA (HIGH BYTE)
tXLPH tPLXH
LOAD ADDRESS (LOW BYTE)
XTAL1
BS1
PAGEL
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure 124 (tDVXH tXHXL tXLDX)
Figure 126. ( )(1)
LOAD ADDRESS (LOW BYTE)
tXLOL
READ DATA (LOW BYTE)
READ DATA (HIGH BYTE)
LOAD ADDRESS (LOW BYTE)
XTAL1
tBVDV
BS1
tOLDV
OE
tOHDZ
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. Figure 124 ( tDVXH tXHXL tXLDX)
Table 128. VCC = 5V 10%
VPP IPP tDVXH tXLXH tXHXL tXLDX tXLWL tXLPH XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 XTAL1 WR XTAL1 PAGEL 67 200 150 67 0 0 11.5 12.5 250 V A ns ns ns ns ns ns
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Table 128. VCC = 5V 10% (Continued)
tPLXH tBVPH tPHPL tPLBX tWLBX tPLWL tBVWL tWLWH tWLRL tWLRH tWLRH_CE tXLOL tBVDV tOLDV tOHDZ Notes: 1. 2. PAGEL XTAL1 PAGEL BS1 PAGEL PAGEL BS1 WR BS2/1 PAGEL WR BS1 WR WR WR RDY/BSY WR RDY/BSY (1) WR RDY/BSY XTAL1 OE BS1 DATA OE DATA OE DATA Flash EEPROM tWLRH tWLRH_CE
(2)
150 67 150 67 67 67 67 150 0 3.7 7.5 0 0

ns ns ns ns ns ns ns ns
1 4.5 9
s ms ms ns
250 250 250
ns ns ns
RESET SPI Flash EEPROM SCK MOSI( ) MISO( ) RESET P260 Table 127 SPI SPI SPI Figure 127. (1)
+1.8 - 5.5V VCC +1.8 - 5.5V(2) MOSI MISO SCK XTAL1 AVCC
RESET
GND
Notes:
1. I XTAL1 2. VCC - 0.3V < AVCC < VCC + 0.3V AVCC 1.8 - 5.5V
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EEPROM MCU EEPROM 0xFF CKSEL (SCK) fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU > fck < 12 MHz 2 CPU fck >= 12 MHz 3 CPU >
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ATmega169 SCK ATmega169 SCK Figure 128 ATmega169 ( Table 130 4 ) 1. RESET SCK 0 VCC GND SCK SCK RESET 2 CPU 2. 20 ms MOSI 3. (0x53) 4 0x53 RESET 4. Flash P260 Table 125 6 LSB 8 tWD_FLASH ( Table 129) Flash 5. EEPROM EEPROM tWD_EEPROM ( Table 129) 0xFF 6. MISO 7. RESET 8. ( ) RESET "1" VCC
Flash
Flash 0xFF Flash 0xFF 0xFF tWD_FLASH 0xFF 0xFF tWD_FLASH Table 129 As a chip-erased device contains 0xFF in all locations, programming of addresses that are meant to contain 0xFF, can be skipped. This does not apply if the EEPROM is reprogrammed without chip erasing the device. In this case, data polling cannot be used for the value 0xFF, and the user will have to wait at least tWD_EEPROM before programming the next byte. See Table 129 for tWD_EEPROM va EEPROM 0xFF 0xFF 0xFF 0xFF EEPROM
EEPROM
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0xFF tWD_EEPROM tWD_EEPROM Table 129 . Table 129. Flash EEPROM
tWD_FUSE tWD_FLASH tWD_EEPROM tWD_ERASE 4.5 ms 4.5 ms 9.0 ms 9.0 ms
Figure 128.
SERIAL DATA INPUT (MOSI) SERIAL DATA OUTPUT (MISO) SERIAL CLOCK INPUT (SCK)
SAMPLE
MSB
LSB
MSB
LSB
Table 130.
1 1010 1100 1010 1100 0010 H000 0100 H000 2 0101 0011 100x xxxx 000a aaaa 000x xxxx 3 xxxx xxxx xxxx xxxx bbbb bbbb xxbb bbbb 4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii RESET EEPROM Flash a:b H( ) o b H( ) i a:b EEPROM a:b o EEPROM a:b o i EEPROM EEPROM a:b EEPROM 0 1 P255 Table 116 . 0 P255 Table 116 b o
EEPROM EEPROM EEPROM ( ) EEPROM( )
0100 1100 1010 0000 1100 0000 1100 0001
000a aaaa 000x xxaa 000x xxaa 0000 0000
bbxx xxxx bbbb bbbb bbbb bbbb 0000 00bb
xxxx xxxx oooo oooo iiii iiii iiii iiii
1100 0010 0101 1000 1010 1100 0011 0000
00xx xxaa 0000 0000 111x xxxx 000x xxxx
bbbb bb00 xxxx xxxx xxxx xxxx xxxx xxbb
xxxx xxxx xxoo oooo 11ii iiii oooo oooo
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Table 130.
RDY/BSY Note: 1 1010 1100 1010 1100 1010 1100 0101 0000 0101 1000 0101 0000 0011 1000 1111 0000 2 1010 0000 1010 1000 1010 0100 0000 0000 0000 1000 0000 1000 000x xxxx 0000 0000 3 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx 4 iiii iiii iiii iiii xxxx xxii oooo oooo oooo oooo oooo oooo oooo oooo xxxx xxxo 0 1 P196 Table 88 0 1 P188 Table 87 0 P256 1 Table 118 0 1 P196 Table 88 0 1 P188 Table 87 0 1 P256 Table 118 o = 1 0
a = b = H = 0 - 1 - o = 4 i = x =
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SPI SPI P288 "SPI " JTAG 4 JTAG :TCKTMSTDI TDOreset JTAG JTAGEN MCUCSR JTD JTD 1 reset JTD JTAG JTAG I/O ISP JTAG JTAG TCK TCK LSB / JTAG 4 16 JTAG OPCODE 16 TDI TDO TAPRun-Test/Idle JTAG Figure 129
JTAG
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Figure 129.
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
AVR_RESET (0xC)
AVR_RESETAVRJTAG AVR TAP 1 1 * Shift-DR TCK
PROG_ENABLE (0x4)
PROG_ENABLEAVRJTAG JTAG 16 * * Shift-DR Update-DR
274
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PROG_COMMANDS (0x5) AVR JTAG JTAG 15 * * * * PROG_PAGELOAD (0x6) Capture-DR Shift-DR TCK Update-DR Flash Run-Test/Idle ( Table 131)
AVR JTAG JTAG Flash 8 Flash 8LSB * * Shift-DRFlash TCK Update-DR .Flash 11 TCK Flash Update-DR AVR PROG_PAGELOAD Update-DR AVR 1 PROG_COMMANDS
PROG_PAGEREAD (0x7)
AVRJTAG JTAGFlash 8Flash 8 LSB * Capture-DR Flash Flash Capture-DR AVR PROG_PAGEREAD Capture-DR AVR 1 PROG_COMMANDS Shift-DR Flash TCK
*
JTAG P274 "JTAG " * * * * Flash
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0 0 ( P24 " " ) P225 Figure 107
16 ( 0b1010_0011_0111_0000) JTAG Figure 130.
TDI
D A T A
0xA370
=
D
Q
Programming Enable
ClockDR & PROG_ENABLE
TDO
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15 JTAG Table 131 Figure 132 Figure 131.
TDI
S T R O B E S
A D D R E S S / D A T A
Flash EEPROM Fuses Lock Bits
TDO
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Table 131. JTAG
1a.
a = , b = , H = 0 - , 1 - , o = , i = , x = TDI 0100011_10000000 0110001_10000000 0110011_10000000 0110011_10000000 0110011_10000000 0100011_00010000 0000111_aaaaaaaa 0000011_bbbbbbbb 0010011_iiiiiiii 0010111_iiiiiiii 0110111_00000000 1110111_00000000 0110111_00000000 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 0110111_00000000 0100011_00000010 0000111_aaaaaaaa 0000011_bbbbbbbb 0110010_00000000 0110110_00000000 0110111_00000000 0100011_00010001 0000111_aaaaaaaa 0000011_bbbbbbbb 0010011_iiiiiiii 0110111_00000000 1110111_00000000 0110111_00000000 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00000011 0000111_aaaaaaaa 0000011_bbbbbbbb TDO xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (9) (1) (9) (9) (1) (9) (2)
1b. 2a. Flash 2b. 2c. 2d. 2e. 2f.
2g. Flash
(1)
2h. 3a. Flash 3b. 3c. 3d.
(2)
4a. EEPROM 4b. 4c. 4d. 4e.
4f. EEPROM
(1)
4g. 5a. EEPROM 5b. 5c.
(2)
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Table 131. JTAG (Continued) (Continued) a = , b = , H = 0 - , 1 - , o = , i = , x =
5d. TDI 0110011_bbbbbbbb 0110010_00000000 0110011_00000000 0100011_01000000 0010011_iiiiiiii 0111011_00000000 0111001_00000000 0111011_00000000 0111011_00000000 0110111_00000000 0010011_iiiiiiii 0110111_00000000 0110101_00000000 0110111_00000000 0110111_00000000 0110111_00000000 0010011_iiiiiiii 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00100000 0010011_11iiiiii 0110011_00000000 0110001_00000000 0110011_00000000 0110011_00000000 0110011_00000000 0100011_00000100 0111010_00000000 0111011_00000000 0111110_00000000 0111111_00000000 0110010_00000000 0110011_00000000 0110110_00000000 0110111_00000000 TDO xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxox_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxoooooo (5) (4) (1) (3) (1)
6a. 6b.
(6)
6c.
6d. 6e. 6f.
(7)
(2) (3) (1)
6g. 6h. 6i.
(7)
(2) (3) (1)
6j. 7a. 7b. (9) 7c.
(2)
7d. 8a. / 8b. 8c. (7) 8d. (8) 8e. (9)
(6)
(2)
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Table 131. JTAG (Continued) (Continued) a = , b = , H = 0 - , 1 - , o = , i = , x =
8f. TDI 0111010_00000000 0111110_00000000 0110010_00000000 0110110_00000000 0110111_00000000 0100011_00001000 0000011_bbbbbbbb 0110010_00000000 0110011_00000000 0100011_00001000 0000011_bbbbbbbb 0110110_00000000 0110111_00000000 0100011_00000000 0110011_00000000 TDO xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx xxxxxxx_oooooooo xxxxxxx_xxxxxxxx xxxxxxx_xxxxxxxx (5)
9a. 9b. 9c. 10a. 10b. 10c. 11a. Notes:
1. ( ) 7 MSB 2. o = "1" 3. "0" = "1" = 4. "0" = "1" = 5. "0" = "1" = 6. P256 Table 118 7. P257 Table 119 8. P257 Table 120 9. P255 Table 116 10. PCMSB EEAMSB(Table 125 Table 126) 11. TDI TDO
280
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Figure 132. /
1 Test-Logic-Reset 0 0 Run-Test/Idle 1 Select-DR Scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 1 0 1 1 Select-IR Scan 0 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 Exit2-IR 1 Update-IR 1 0 0 1 0 1
Flash
Flash Flash / Flash Flash Flash / Flash88 Update-DR 11 TCK Flash Update-DR AVR PROG_PAGELOAD UpdateDR AVR 1 PROG_COMMANDS Flash Capture-DR Flash Capture-DR AVR PROG_PAGEREAD Capture-DR AVR 1 PROG_COMMANDS
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Figure 133. Flash
STROBES
TDI
State Machine
ADDRESS
Flash EEPROM Fuses Lock Bits
D A T A
TDO
Flash TCK Flash 8 TAP Update-DR TAP Run-Test/Idle TCK Update-DR 11 TCK "1a" "1b" Table 131 1. JTAG AVR_RESET 1 Reset 2. PROG_ENABLE 0b1010_0011_0111_0000 1. JTAG PROG_COMMANDS 2. 11a 3. PROG_ENABLE 0b0000_0000_0000_0000 4. JTAG AVR_RESET 0 Reset 1. JTAG PROG_COMMANDS 2. 1a 3. 1b tWLRH_CE( P267 Table 128 ) Flash Flash P283 " " 1. JTAG PROG_COMMANDS 2. 2a Flash 3. 2b 4. 2c 5. 2d 2e 2f 6. 4 5 7. 2g
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ATmega169V/L
8. 2h Flash tWLRH( P267 Table 128 ) 9. 3 7 PROG_PAGELOAD 1. JTAG PROG_COMMANDS 2. 2a Flash 3. 2b 2c PCWORD( P260 Table 125 ) 0 4. JTAG PROG_PAGELOAD 5. LSB MSB Update-DR Flash Flash 1 6. JTAG PROG_COMMANDS 7. 2g 8. 2h Flash tWLRH( P267 Table 128 ) 9. 3 8 Flash 1. JTAG PROG_COMMANDS 2. 3a Flash 3. 3b 3c 4. 3d 5. 3 4 PROG_PAGEREAD 1. JTAG PROG_COMMANDS 2. 3a Flash 3. 3b 3c PCWORD( P260 Table 125 ) 0 4. JTAG PROG_PAGEREAD 5. LSB MSB Capture-DR Flash 1 Capture-DR shift-DR 6. JTAG PROG_COMMANDS 7. 3 6 EEPROM EEPROM P283 " " 1. JTAG PROG_COMMANDS 2. 4a EEPROM 3. 4b 4. 4c 5. 4d 4e 6. 4 5 7. 4f 8. 4g EEPROM tWLRH( P267 Table 128 ) 9. 3 8
283
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EEPROM PROG_PAGELOAD EEPROM 1. JTAG PROG_COMMANDS 2. 5a EEPROM 3. 5b 5c 4. 5d 5. 3 4 EEPROM PROG_PAGEREAD Fuse 1. JTAG PROG_COMMANDS 2. 6a 3. 6b 0 4. 6c 5. 6d tWLRH( P267 Table 128 ) 6. 6e 0 1 7. 6f 8. 6g tWLRH( P267 Table 128 ) 1. JTAG PROG_COMMANDS 2. 7a 3. 7b 0 4. 7c 5. 7d tWLRH( P267 Table 128 ) 1. JTAG PROG_COMMANDS 2. 8a / 3. 8e 8b 8c 8d 1. JTAG PROG_COMMANDS 2. 9a 3. 9b 0x00 4. 9c 5. 0x01 0x02 3 4 1. JTAG PROG_COMMANDS 2. 10a 3. 10b 0x00 4. 10c
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*
........................................................ -55C to +125C ........................................................ -65C to +150C RESET.............-0.5V to VCC+0.5V RESET ...................................-0.5V to +13.0V .................................................................... 6.0V I/O ......................................... 40.0 mA *NOTICE: " "
VCC GND ................................ 200.0 mA
VIL VIL1 VIH VIH1 VIH2 VOL VOL1 VOH VOH1 IIL IIH RRST RPU
TA = -40C-85C, VCC = 1.8V-5.5V ( )
XTAL1 XTAL1 XTAL1 RESET XTAL1 RESET (3) A, C, D, E, F, G (3) B (4) A, C, D, E, F, G (4) B I/O I I/O Reset I/O VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VCC = 1.8V - 5.5V VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VCC = 1.8V - 2.4V VCC = 2.4V - 5.5V VCC = 1.8V - 5.5V IOL = 10mA, VCC = 5V IOL = 5mA, VCC = 3V IOL = 20mA, VCC = 5V IOL = 10mA, VCC = 3V IOH = -10mA, VCC = 5V IOH = -5mA, VCC = 3V IOH = -20mA, VCC = 5V IOH = -10mA, VCC = 3V VCC = 5.5V ( ) VCC = 5.5V ( ) 30 20 4.2 2.3 4.2 2.3 1 1 60 50 -0.5 -0.5 -0.5 0.7VCC(2) 0.6VCC(2) 0.8VCC(2) 0.7VCC(2) 0.9VCC(2) 0.2VCC(1) 0.3VCC(1) 0.1VCC(1) VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.7 0.5 0.7 0.5 V V V V V V V V V A A k k
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TA = -40C-85C, VCC = 1.8V-5.5V ( ) (Continued)
1MHz, VCC = 2V (ATmega169V) 4MHz, VCC = 3V (ATmega169L) 8MHz, VCC = 5V (ATmega169) 1MHz, VCC = 2V (ATmega169V) 4MHz, VCC = 3V (ATmega169L) 8MHz, VCC = 5V (ATmega169) VACIO IACLK tACID Note: WDT VCC = 3V WDT VCC = 3V VCC = 5V Vin = VCC/2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50 750 500 <8 <1 <10 0.25 0.55 3.5 12 0.5 1.5 5.5 10 2 40 50 mA mA mA mA mA mA A A mV nA ns
ICC
1. " " 2. " " 3. ( ) I/O (20 mA CC = 5V 10 mAVCC = 3V V 10 mA VCC = 5V 5 mA VCC = 3V) TQFP MLF 1] IOL 400 mA 2] A0 - A7, C4 - C7, G2 IOL 100 mA 3] B0 - B7, E0 - E7, G3 - G5 IOL 100 mA 4] D0 - D7, C0 - C3, G0 - G1 IOL 100 mA 5] F0 - F7 IOL 100 mA IOL VOL 4. ( ) I/O (20 mA CC = 5V 10 mAVCC = 3V V 10 mA VCC = 5V 5 mA VCC = 3V) TQFP MLF 1] IOL 400 mA 2] A0 - A7, C4 - C7, G2 IOL 100 mA 3] B0 - B7, E0 - E7, G3 - G5 IOL 100 mA 4] D0 - D7, C0 - C3, G0 - G1 IOL 100 mA 5] F0 - F7 IOL 100 mA IOH VOH
286
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ATmega169V/L
Figure 134.
V IH1 V IL1
Table 132.
VCC=1.8-5.5V 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL 0 1000 400 400 2.0 2.0 2 1 VCC=2.7-5.5V 0 125 50 50 1.6 1.6 2 8 VCC=4.5-5.5V 0 62.5 25 25 0.5 0.5 2 16 MHz ns ns ns s s %
tCLCL
SPI
Figure 135 Figure 136 Table 133. SPI
1 2 3 4 5 6 7 8 9 10 11 12 SCK SCK SCK SCK SCK SS SCK SCK
(1)

50% 3.6 10 10 0.5 * tsck 10 10 15

ns
4 * tck 2 * tck 1.6 s
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Table 133. SPI
13 14 15 16 17 18 Note: SCK SCK SS SS 20 10 10 tck 15 ns
SS SCK 20 * tck 1. SPI SCK fCK < 12 MHz - 2 tCLCL fCK > 12 MHz - 3 tCLCL
Figure 135. SPI ( )
SS
6 1
SCK (CPOL = 0)
2 2
SCK (CPOL = 1)
4 5 3
MISO (Data Input)
MSB 7
...
LSB 8
MOSI (Data Output)
MSB
...
LSB
Figure 136. SPI ( )
SS
9 10 16
SCK (CPOL = 0)
11 11
SCK (CPOL = 1)
13 14 12
MOSI (Data Input)
MSB 15
...
LSB 17
MISO (Data Output)
MSB
...
LSB
X
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ADC --
Table 134. ADC
VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 1 MHz ( INL DNL ) VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 1 MHz (INL) VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 200 kHz VREF = 4V, VCC = 4V, ADC = 200 kHz 1.0 13 50 VCC - 0.3 1.0 1.0 GND 0 38,5 4 1.1 32 100 1.2 10 8 2 2.5 Bits Bits LSB
4.5
LSB
2
LSB
4.5
LSB
0.5
LSB
(DNL)
0.25
LSB
2
LSB
AVCC VREF VIN VINT RREF RAIN Note: 1. VDIFF VREF
2 260 1000 VCC + 0.3 AVCC AVCC - 0.5 VREF AVCC
(1)
LSB s kHz V V V V V kHz kHz V k M
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LCD --
Table 135. LCD
ILCD RLCD LCD LCD COM SEG COM SEG 100 10 A k
290
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ATmega169 --
I/O I/O I/O I/O CL*VCC*f CL = VCC = f = I/O Figure 137. (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 2 1.8 1.6 1.4 1.2 ICC (mA) 1
5.5V
5.0V 4.5V 4.0V 3.3V
0.8 0.6 0.4 0.2 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1
2.7V 1.8V
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Figure 138. (1 - 20 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz 30
5.5V
25
5.0V 4.5V
20 ICC (mA)
15
4.0V 3.3V 2.7V 1.8V
10
5
0 0 2 4 6 8 10 Frequency (MHz) 12 14 16 18 20
Figure 139. VCC ( RC 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz 14
12
85C 25C -40C
10
ICC (mA)
8
6
4
2
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
292
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Figure 140. VCC ( RC CKDIV8 1 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, CKDIV8 PROGRAMMED, 1 MHz 2.5
2
85C 25C -40C
1.5 ICC (mA) 1 0.5 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 141. VCC (32 kHz )
ACTIVE SUPPLY CURRENT vs. VCC
32kHz EXTERNAL OSCILLATOR 100 90 80 70 60 ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85C 25C
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Figure 142. (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz 0.8 0.7 0.6 0.5 ICC (mA) 0.4
5.5V
5.0V 4.5V 4.0V 3.3V
0.3 0.2 0.1 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1
2.7V 1.8V
Figure 143. (1 - 20 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz 16 14 12 10 ICC (mA) 8 6 4 2 0 0 2 4
5.5V
5.0V 4.5V
4.0V
3.3V 2.7V 1.8V
6 8 10 Frequency (MHz) 12 14 16 18 20
294
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ATmega169V/L
Figure 144. VCC ( RC 8 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz 7
6
85C 25C -40C
5
ICC (mA)
4
3
2
1
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 145. VCC ( RC CKDIV8 1 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, CKDIV8 PROGRAMMED, 1 MHz 1 0.9 0.8 0.7 0.6 ICC (mA) 0.5 0.4 0.3 0.2 0.1 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85C 25C -40C
295
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Figure 146. VCC (32 kHz )
IDLE SUPPLY CURRENT vs. VCC
32kHz EXTERNAL OSCILLATOR 50 45 40 35 30 ICC (uA) 25 20 15 10 5 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85C 25C
Figure 147. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED 3.5
3
85C
2.5
ICC (uA)
2
-40C
1.5
25C
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
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Figure 148. VCC ( )
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED 20 18 16 14 12 ICC (uA) 10 8 6 4 2 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85C -40C 25C
Figure 149. VCC ( )
POWER-SAVE SUPPLY CURRENT vs. V CC
WATCHDOG TIMER DISABLED 30
25
20 ICC (uA)
85C 25C
15
10
5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
297
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Standby
Figure 150. Standby VCC (455 kHz )
STANDBY SUPPLY CURRENT vs. V CC
455 kHz RESONATOR, WATCHDOG TIMER DISABLED 70 60 50 40 30 20 10 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 151. Standby VCC (1 MHz )
ICC (uA)
STANDBY SUPPLY CURRENT vs. V CC
1 MHz RESONATOR, WATCHDOG TIMER DISABLED 60
50
40 ICC (uA)
30
20
10
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
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Figure 152. Standby VCC (2 MHz )
STANDBY SUPPLY CURRENT vs. V CC
2 MHz RESONATOR, WATCHDOG TIMER DISABLED 90 80 70 60 ICC (uA) 50 40 30 20 10 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 153. Standby VCC (2 MHz Xtal )
STANDBY SUPPLY CURRENT vs. V CC
2 MHz XTAL, WATCHDOG TIMER DISABLED 80 70 60 50 ICC (uA) 40 30 20 10 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
299
2514I-AVR-10/03
Figure 154. Standby VCC (4 MHz )
STANDBY SUPPLY CURRENT vs. V CC
4 MHz RESONATOR, WATCHDOG TIMER DISABLED 140 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 155. Standby VCC (4 MHz Xtal )
ICC (uA)
STANDBY SUPPLY CURRENT vs. V CC
4 MHz XTAL, WATCHDOG TIMER DISABLED 140 120 100 80 60 40 20 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
300
ATmega169V/L
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ICC (uA)
ATmega169V/L
Figure 156. Standby VCC (6 MHz )
STANDBY SUPPLY CURRENT vs. V CC
6 MHz RESONATOR, WATCHDOG TIMER DISABLED 160 140 120 100 ICC (uA) 80 60 40 20 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 157. Standby VCC (6 MHz )
STANDBY SUPPLY CURRENT vs. V CC
6 MHz XTAL, WATCHDOG TIMER DISABLED 180 160 140 120 ICC (uA) 100 80 60 40 20 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
301
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Figure 158. I/O (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5V 160
85C
140 120 100
25C -40C
IIO (uA)
80 60 40 20 0 0 1 2 3 VIO (V) 4 5
Figure 159. I/O (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7V 90 80
85C
70 60 IIO (uA) 50 40 30 20 10 0 0
25C -40C
0.5
1
1.5 VIO (V)
2
2.5
3
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Figure 160. I/O (VCC = 1.8V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 1.8V 60
50
85C
40 IOP (uA)
25C
-40C
30
20
10
0 0 0.2 0.4 0.6 0.8 1 VOP (V) 1.2 1.4 1.6 1.8 2
Figure 161. (Reset) Reset (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 5V 120
-40C
100
25C
80
85C
IRESET (uA)
60
40
20
0 0 1 2 3 VRESET (V) 4 5
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Figure 162. (Reset) Reset (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 2.7V 70
-40C
60
25C 85C
50 IRESET (uA)
40
30
20
10
0 0 0.5 1 1.5 VRESET (V) 2 2.5 3
Figure 163. (Reset) Reset (VCC = 1.8V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 1.8V 40
-40C
35
25C
30
85C
IRESET (uA) 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 VRESET (V) 1.2 1.4 1.6 1.8 2
304
ATmega169V/L
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Figure 164. I/O A, C, D, E, F, G (VCC = 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G
Vcc = 5V 70 60 50 IOH (mA) 40 30 20 10 0 0 1 2 3 VOH (V) 4 5 6
-40C 25C 85C
Figure 165. I/O A, C, D, E, F, G (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G
Vcc = 2.7V 25
-40C
20
25C 85C
IOH (mA)
15
10
5
0 0 0.5 1 1.5 VOH (V) 2 2.5 3
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Figure 166. I/O A, C, D, E, F, G (VCC = 1.8V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G
Vcc = 1.8V 8 7
-40C
25C
6 5 IOH (mA) 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 VOH (V) 1.2 1.4 1.6 1.8 2
85C
Figure 167. I/O B (VCC= 5V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B
Vcc = 5V 80 70 60 50 IOH (mA) 40 30 20 10 0 0 1 2 3 VOH (V) 4
-40C 25C 85C
306
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ATmega169V/L
Figure 168. I/O B (VCC = 2.7V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B
Vcc = 2.7V 35 30 25 IOH (mA) 20 15 10 5 0 0 0.5 1 1.5 VOH (V) 2 2.5 3
-40C 25C 85C
Figure 169. I/O B (VCC = 1.8V)
I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE, PORT B
Vcc = 1.8V 10 9
-40C 85C
25C
8 7
IOH (mA)
6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 VOH (V) 1.2 1.4 1.6 1.8 2
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Figure 170. I/O A, C, D, E, F, G (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G
Vcc = 5V 50 45 40 35 IOL (mA) 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
-40C 25C 85C
Figure 171. I/O A, C, D, E, F, G (VCC = 2.7V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G
Vcc = 2.7V 20 18 16 14 IOL (mA) 12 10 8 6 4 2 0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
-40C 25C 85C
308
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Figure 172. I/O A, C, D, E, F, G (VCC = 1.8V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORTS A, C, D, E, F, G
Vcc = 1.8V 7
-40C
6
25C
5 IOL (mA) 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
85C
Figure 173. I/O B (VCC = 5V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B
Vcc = 5V 90 80 70 60 IOL (mA) 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
-40C 25C 85C
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2514I-AVR-10/03
Figure 174. I/O B (VCC = 2.7V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B
Vcc = 2.7V 35 30 25 IOL (mA) 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
-40C 25C 85C
Figure 175. I/O B (VCC = 1.8V)
I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE, PORT B
Vcc = 1.8V 12
10
-40C 25C
8 IOL (mA)
85C
6
4
2
0 0 0.2 0.4 0.6 0.8 1 VOL (V) 1.2 1.4 1.6 1.8 2
310
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Figure 176. I/O VCC (VIH, I/O "1")
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, I/O PIN READ AS '1' 3
85C 25C -40C
2.5
2 Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 177. I/O VCC (VIL, I/O "0")
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, I/O PIN READ AS '0' 3
2.5
85C 25C -40C
2 Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
311
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Figure 178. I/O VCC
I/O PIN INPUT HYSTERESIS vs. VCC
0.6
-40C
0.5
25C
0.4 Threshold (V)
85C
0.3
0.2
0.1
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 179. Reset VCC (VIH,Reset "1")
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, RESET PIN READ AS '1' 2.5
2
Threshold (V)
1.5
-40C 25C 85C
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
312
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Figure 180. Reset VCC (VIL,Reset "0")
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, RESET PIN READ AS '0' 2.5
85C 25C -40C
2
Threshold (V)
1.5
1
0.5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 181. Reset VCC
RESET INPUT PIN HYSTERESIS vs. VCC
0.7
0.6
-40C
0.5 Threshold (V)
25C
0.4
0.3
85C
0.2
0.1
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
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BOD
Figure 182. BOD (BOD 4.3V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 4.3V 4.6
4.5
Rising VCC
4.4 Threshold (V)
Falling VCC
4.3
4.2
4.1
4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C)
Figure 183. BOD (BOD 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 2.7V 3
2.9
Rising VCC
2.8 Threshold (V)
2.7
Falling VCC
2.6
2.5
2.4 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C)
314
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Figure 184. BOD (BOD 1.8V)
BOD THRESHOLDS vs. TEMPERATURE
BODLEVEL IS 1.8V 2.1
2
1.9 Threshold (V)
Rising VCC
1.8
Falling VCC
1.7
1.6
1.5 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 Temperature (C)
Figure 185. VCC
BANDGAP VOLTAGE vs. VCC
1.14
1.13 Bandgap Voltage (V)
1.12
1.11
85C 25C -40C
1.1
1.09
1.08 1.5 2 2.5 3 3.5 Vcc (V) 4 4.5 5 5.5
315
2514I-AVR-10/03
Figure 186. (VCC = 5V)
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE
VCC = 5V 0.008
85C
0.006 Comparator Offset Voltage (V)
25C -40C
0.004
0.002
0
-0.002
-0.004 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Common Mode Voltage (V)
Figure 187. (VCC = 2.7V)
ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE
VCC = 2.7V 0.003
85C
0.002 Comparator Offset Voltage (V) 0.001 0 -0.001 -0.002 -0.003 -0.004 0 0.5 1 1.5 Common Mode Voltage (V) 2 2.5 3
25C -40C
316
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Figure 188. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. VCC
1200 1150 1100 1050 FRC (kHz) 1000 950 900 850 800 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
-40C 25C 85C
Figure 189. 8 MHz RC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.8 8.6 8.4 8.2 8 7.8 7.6 7.4 7.2 -60 -40 -20 0 20 Ta (C) 40 60 80 100
FRC (MHz)
1.8V 2.7V 4.0V 5.5V
317
2514I-AVR-10/03
Figure 190. 8 MHz RC VCC
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. VCC
10 9.5 9 8.5 FRC (MHz) 8 7.5 7 6.5 6 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85C 25C -40C
Figure 191. 8 MHz RC Osccal
CALIBRATED 8MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
13 12 11 10 FRC (MHz) 9 8 7 6 5 4 3 0 16 32 48 64 OSCCAL VALUE 80 96 112
318
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Figure 192. BOD VCC
BROWNOUT DETECTOR CURRENT vs. V CC
30
25
-40C 85C 25C
20 ICC (uA)
15
10
5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 193. ADC VCC (AREF = AVCC)
ADC CURRENT vs. VCC
AREF = AVCC 350
300
-40C 25C 85C
250
ICC (uA)
200
150
100
50
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
319
2514I-AVR-10/03
Figure 194. AREF VCC
AREF EXTERNAL REFERENCE CURRENT vs. V CC
160 140 120 100 IAREF (uA) 80 60 40 20 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85C 25C -40C
Figure 195. 32 kHZ TOSC VCC ( )
32kHz TOSC CURRENT vs. VCC
WATCHDOG TIMER DISABLED 25
20
85C 25C
15 ICC (uA) 10 5 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
320
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Figure 196. VCC
WATCHDOG TIMER CURRENT vs. VCC
16 14 12 10 ICC (uA) 8 6 4 2 0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
85C 25C -40C
Figure 197. VCC
ANALOG COMPARATOR CURRENT vs. VCC
120
100
-40C 25C 85C
80 ICC (uA)
60
40
20
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
321
2514I-AVR-10/03
Figure 198. VCC
PROGRAMMING CURRENT vs. Vcc
25
20
-40C 25C
15 ICC (mA)
85C
10
5
0 1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
Figure 199. VCC (0.1 - 1.0 MHz )
RESET SUPPLY CURRENT vs. FREQUENCY
0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 0.18 0.16 0.14 0.12 ICC (mA) 0.1 0.08 0.06 0.04 0.02 0 0 0.1 0.2 0.3 0.4 0.5 Frequency (MHz) 0.6 0.7 0.8 0.9 1
5.5V
5.0V 4.5V 4.0V 3.3V 2.7V 1.8V
322
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Figure 200. VCC (1 - 20 MHz )
RESET SUPPLY CURRENT vs. FREQUENCY
1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP 3.5 3 2.5 ICC (mA) 2 1.5 1 0.5 0 0 2 4
5.5V
5.0V 4.5V 4.0V 3.3V 2.7V 1.8V
6 8 10 Frequency (MHz) 12 14 16 18 20
Figure 201. VCC
RESET PULSE WIDTH vs. VCC
2500
2000
Pulsewidth (ns)
1500
1000
500
85C 25C -40C
1.5 2 2.5 3 3.5 VCC (V) 4 4.5 5 5.5
0
323
2514I-AVR-10/03
(0xFF) (0xFE) (0xFD) (0xFC) (0xFB) (0xFA) (0xF9) (0xF8) (0xF7) (0xF6) (0xF5) (0xF4) (0xF3) (0xF2) (0xF1) (0xF0) (0xEF) (0xEE) (0xED) (0xEC) (0xEB) (0xEA) (0xE9) (0xE8) (0xE7) (0xE6) (0xE5) (0xE4) (0xE3) (0xE2) (0xE1) (0xE0) (0xDF) (0xDE) (0xDD) (0xDC) (0xDB) (0xDA) (0xD9) (0xD8) (0xD7) (0xD6) (0xD5) (0xD4) (0xD3) (0xD2) (0xD1) (0xD0) (0xCF) (0xCE) (0xCD) (0xCC) (0xCB) (0xCA) (0xC9) (0xC8) (0xC7) (0xC6) (0xC5) (0xC4) (0xC3) (0xC2) (0xC1) (0xC0)
LCDDR18 LCDDR17 LCDDR16 LCDDR15 LCDDR13 LCDDR12 LCDDR11 LCDDR10 LCDDR8 LCDDR7 LCDDR6 LCDDR5 LCDDR3 LCDDR2 LCDDR1 LCDDR0 LCDCCR LCDFRR LCDCRB LCDCRA UDR UBRRH UBRRL UCSRC UCSRB UCSRA
7
- - SEG323 SEG315 SEG307 - - SEG223 SEG215 SEG207 - - SEG123 SEG115 SEG107 - - SEG023 SEG015 SEG007 - - - - - - LCDCS LCDEN - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
6
- - SEG322 SEG314 SEG306 - - SEG222 SEG214 SEG206 - - SEG122 SEG114 SEG106 - - SEG022 SEG014 SEG006 - - - - - LCDPS2 LCD2B LCDAB - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
5
- - SEG321 SEG313 SEG305 - - SEG221 SEG213 SEG205 - - SEG121 SEG113 SEG105 - - SEG021 SEG013 SEG005 - - - - - LCDPS1 LCDMUX1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
4
- - SEG320 SEG312 SEG304 - - SEG220 SEG212 SEG204 - - SEG120 SEG112 SEG104 - - SEG020 SEG012 SEG004 - - - - - LCDPS0 LCDMUX0 LCDIF - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
3
- - SEG319 SEG311 SEG303 - - SEG219 SEG211 SEG203 - - SEG119 SEG111 SEG103 - - SEG019 SEG011 SEG003 - - - - LCDCC3 - - LCDIE - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
2
- - SEG318 SEG310 SEG302 - - SEG218 SEG210 SEG202 - - SEG118 SEG110 SEG102 - - SEG018 SEG010 SEG002 - - - - LCDCC2 LCDCD2 LCDPM2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1
- - SEG317 SEG309 SEG301 - - SEG217 SEG209 SEG201 - - SEG117 SEG109 SEG101 - - SEG017 SEG09 SEG001 - - - - LCDCC1 LCDCD1 LCDPM1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
0
- SEG324 SEG316 SEG308 SEG300 - SEG224 SEG216 SEG208 SEG200 - SEG124 SEG116 SEG108 SEG100 - SEG024 SEG016 SEG008 SEG000 - - - - LCDCC0 LCDCD0 LCDPM0 LCDBL - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
216 216 216 216 216 216 216 216 216 216 216 216 216 216 216 216
216 214 212 212
USART I/O USART USART - - RXCIE RXC - UMSEL TXCIE TXC - UPM1 UDRIE UDRE - UPM0 RXEN FE - USBS TXEN DOR - UCSZ1 UCSZ2 UPE - UCSZ0 RXB8 U2X - UCPOL TXB8 MPCM
160 165 165 161 161 161
324
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
(0xBF) (0xBE) (0xBD) (0xBC) (0xBB) (0xBA) (0xB9) (0xB8) (0xB7) (0xB6) (0xB5) (0xB4) (0xB3) (0xB2) (0xB1) (0xB0) (0xAF) (0xAE) (0xAD) (0xAC) (0xAB) (0xAA) (0xA9) (0xA8) (0xA7) (0xA6) (0xA5) (0xA4) (0xA3) (0xA2) (0xA1) (0xA0) (0x9F) (0x9E) (0x9D) (0x9C) (0x9B) (0x9A) (0x99) (0x98) (0x97) (0x96) (0x95) (0x94) (0x93) (0x92) (0x91) (0x90) (0x8F) (0x8E) (0x8D) (0x8C) (0x8B) (0x8A) (0x89) (0x88) (0x87) (0x86) (0x85) (0x84) (0x83) (0x82) (0x81) (0x80) (0x7F) (0x7E)
USIDR USISR USICR ASSR OCR2A TCNT2 TCCR2A OCR1BH OCR1BL OCR1AH OCR1AL ICR1H ICR1L TCNT1H TCNT1L TCCR1C TCCR1B TCCR1A DIDR1 DIDR0
7
- - - - - USISIF USISIE - - - -
6
- - - - - USIOIF USIOIE - - -
5
- - - - - USIPF USIWM1 - - - -
4
- - - - - USIDC USIWM0 - EXCLK - -
3
- - - - -
2
- - - - - USICNT2 USICS0 - TCN2UB - -
1
- - - - - USICNT1 USICLK - OCR2UB - -
0
- - - - -
USI USICNT3 USICS1 - AS2 - - USICNT0 USITC - TCR2UB - -
176 176 177 131
/ 2 A / 2(8 ) - FOC2A - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - WGM20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - COM2A1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - COM2A0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - WGM21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CS22 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CS21 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - CS20 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
130 130 128
/ 1 B / 1 B / 1 A / 1 A / 1 / 1 / 1 / 1 - FOC1A ICNC1 COM1A1 - ADC7D - FOC1B ICES1 COM1A0 - ADC6D - - - COM1B1 - ADC5D - - WGM13 COM1B0 - ADC4D - - WGM12 - - ADC3D - - CS12 - - ADC2D - - CS11 WGM11 AIN1D ADC1D - - CS10 WGM10 AIN0D ADC0D
116 116 116 116 122 122 115 115 115 114 112 183 201
325
2514I-AVR-10/03
(0x7D) (0x7C) (0x7B) (0x7A) (0x79) (0x78) (0x77) (0x76) (0x75) (0x74) (0x73) (0x72) (0x71) (0x70) (0x6F) (0x6E) (0x6D) (0x6C) (0x6B) (0x6A) (0x69) (0x68) (0x67) (0x66) (0x65) (0x64) (0x63) (0x62) (0x61) (0x60) 0x3F (0x5F) 0x3E (0x5E) 0x3D (0x5D) 0x3C (0x5C) 0x3B (0x5B) 0x3A (0x5A) 0x39 (0x59) 0x38 (0x58) 0x37 (0x57) 0x36 (0x56) 0x35 (0x55) 0x34 (0x54) 0x33 (0x53) 0x32 (0x52) 0x31 (0x51) 0x30 (0x50) 0x2F (0x4F) 0x2E (0x4E) 0x2D (0x4D) 0x2C (0x4C) 0x2B (0x4B) 0x2A (0x4A) 0x29 (0x49) 0x28 (0x48) 0x27 (0x47) 0x26 (0x46) 0x25 (0x45) 0x24 (0x44) 0x23 (0x43) 0x22 (0x42) 0x21 (0x41) 0x20 (0x40) 0x1F (0x3F) 0x1E (0x3E) 0x1D (0x3D) 0x1C (0x3C)
ADMUX ADCSRB ADCSRA ADCH ADCL TIMSK2 TIMSK1 TIMSK0 PCMSK1 PCMSK0 EICRA OSCCAL CLKPR WDTCR SREG SPH SPL SPMCSR MCUCR MCUSR SMCR OCDR ACSR SPDR SPSR SPCR GPIOR2 GPIOR1 OCR0A TCNT0 TCCR0A GTCCR EEARH EEARL EEDR EECR GPIOR0 EIMSK EIFR
7
- REFS1 - ADEN
6
- REFS0 ACME ADSC
5
- ADLAR - ADATE
4
- MUX4 - ADIF
3
- MUX3 - ADIE
2
- MUX2 ADTS2 ADPS2
1
- MUX1 ADTS1 ADPS1
0
- MUX0 ADTS0 ADPS0
197 181, 200 199 200 200
ADC ADC - - - - - - - - - - - PCINT15 PCINT7 - - - - - - - - CLKPCE - I SP15 SP7 - - - - - - - - - - - PCINT14 PCINT6 - - - - - - - - - - T SP14 SP6 - - - - - - - - ICIE1 - - PCINT13 PCINT5 - - - - - - - - - - H SP13 SP5 - - - - - - - - - - - PCINT12 PCINT4 - - - - - - - - - WDCE S SP12 SP4 - - - - CLKPS3 WDE V SP11 SP3 - - - - CLKPS2 WDP2 N SP10 SP2 - - - - CLKPS1 WDP1 Z SP9 SP1 - - - - CLKPS0 WDP0 C SP8 SP0 - - - - - - - - - - - PCINT11 PCINT3 - - - - - - - - - - - - OCIE1B - - PCINT10 PCINT2 - - - - - - - - - - - OCIE2A OCIE1A OCIE0A - PCINT9 PCINT1 - ISC01 - - - - - - - - - TOIE2 TOIE1 TOIE0 - PCINT8 PCINT0 - ISC00 - -
133 117 89 78 78 76
28
30 42 9 11 11
SPMIE - JTD - - - IDRD/OCD ACD - SPIF SPIE
RWWSB - - - - - OCDR6 ACBG - WCOL SPE
- - - - - - OCDR5 ACO - - DORD
RWWSRE - PUD JTRF - - OCDR4 ACI - - MSTR
BLBSET - - WDRF SM2 - OCDR3 ACIE -
PGWRT - - BORF SM1 - OCDR2 ACIC - - CPHA
PGERS - IVSEL EXTRF SM0 - OCDR1 ACIS1 - - SPR1
SPMEN - IVCE PORF SE - OCDR0 ACIS0 -
246 227 228 32 223 181 141
SPI - CPOL I/O 2 I/O 1 - - - - - - - - - - - - - - - - SPI2X SPR0
141 139 22 22
/ 0 A / 0 (8 ) - FOC0A TSM - - WGM00 - - - COM0A1 - - - COM0A0 - - - WGM01 - - - CS02 - - - CS01 PSR2 - - CS00 PSR10 EEAR8
89 91 89 91 18 18 18 EEMWE - - EEWE - - EERE INT0 INTF0 18 22 77 77
EEPROM EEPROM - PCIE1 PCIF1 - PCIE0 PCIF0 - - - - - - EERIE I/O 0 - -
326
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
0x1B (0x3B) 0x1A (0x3A) 0x19 (0x39) 0x18 (0x38) 0x17 (0x37) 0x16 (0x36) 0x15 (0x35) 0x14 (0x34) 0x13 (0x33) 0x12 (0x32) 0x11 (0x31) 0x10 (0x30) 0x0F (0x2F) 0x0E (0x2E) 0x0D (0x2D) 0x0C (0x2C) 0x0B (0x2B) 0x0A (0x2A) 0x09 (0x29) 0x08 (0x28) 0x07 (0x27) 0x06 (0x26) 0x05 (0x25) 0x04 (0x24) 0x03 (0x23) 0x02 (0x22) 0x01 (0x21) 0x00 (0x20)
TIFR2 TIFR1 TIFR0 PORTG DDRG PING PORTF DDRF PINF PORTE DDRE PINE PORTD DDRD PIND PORTC DDRC PINC PORTB DDRB PINB PORTA DDRA PINA
7
- - - - - - - - - - PORTF7 DDF7 PINF7 PORTE7 DDE7 PINE7 PORTD7 DDD7 PIND7 PORTC7 DDC7 PINC7 PORTB7 DDB7 PINB7 PORTA7 DDA7 PINA7
6
- - - - - - - - - - PORTF6 DDF6 PINF6 PORTE6 DDE6 PINE6 PORTD6 DDD6 PIND6 PORTC6 DDC6 PINC6 PORTB6 DDB6 PINB6 PORTA6 DDA6 PINA6
5
- - - - - ICF1 - - - PING5 PORTF5 DDF5 PINF5 PORTE5 DDE5 PINE5 PORTD5 DDD5 PIND5 PORTC5 DDC5 PINC5 PORTB5 DDB5 PINB5 PORTA5 DDA5 PINA5
4
- - - - - - - PORTG4 DDG4 PING4 PORTF4 DDF4 PINF4 PORTE4 DDE4 PINE4 PORTD4 DDD4 PIND4 PORTC4 DDC4 PINC4 PORTB4 DDB4 PINB4 PORTA4 DDA4 PINA4
3
- - - - - - - PORTG3 DDG3 PING3 PORTF3 DDF3 PINF3 PORTE3 DDE3 PINE3 PORTD3 DDD3 PIND3 PORTC3 DDC3 PINC3 PORTB3 DDB3 PINB3 PORTA3 DDA3 PINA3
2
- - - - - OCF1B - PORTG2 DDG2 PING2 PORTF2 DDF2 PINF2 PORTE2 DDE2 PINE2 PORTD2 DDD2 PIND2 PORTC2 DDC2 PINC2 PORTB2 DDB2 PINB2 PORTA2 DDA2 PINA2
1
- - - - OCF2A OCF1A OCF0A PORTG1 DDG1 PING1 PORTF1 DDF1 PINF1 PORTE1 DDE1 PINE1 PORTD1 DDD1 PIND1 PORTC1 DDC1 PINC1 PORTB1 DDB1 PINB1 PORTA1 DDA1 PINA1
0
- - - - TOV2 TOV1 TOV0 PORTG0 DDG0 PING0 PORTF0 DDF0 PINF0 PORTE0 DDE0 PINE0 PORTD0 DDD0 PIND0 PORTC0 DDC0 PINC0 PORTB0 DDB0 PINB0 PORTA0 DDA0 PINA0
141 118 89 75 73 75 74 74 75 72 74 74 74 74 74 73 71 72 73 73 73 71 71 73
Note:
1. 0 I/O 2. SBI CBI 0x00 - 0x1F I/O SBIS SBIC 3. 1 AVR CBI SBI CBI SBI 0x00 - 0x1F 4. I/OINOUT 0x00 - 0x3F LD STI/O I/O 0x20 ATmega169 I/O IN/OUT 64 ST/STS/STD LD/LDS/LDD SRAM 0x60 - 0xFF I/O
327
2514I-AVR-10/03

ADD ADC ADIW SUB SUBI SBC SBCI SBIW AND ANDI OR ORI EOR COM NEG SBR CBR INC DEC TST CLR SER MUL MULS MULSU FMUL FMULS FMULSU Rd, Rr Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, K Rd, Rr Rd, K Rd, Rr Rd, K Rd, Rr Rd Rd Rd, K Rd, K Rd Rd Rd Rd Rd Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr Rd, Rr 1 2 Rd Rd + Rr Rd Rd + Rr + C Rd+1:Rd Rd+1:Rd + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rd+1:Rd Rd+1:Rd - K Rd Rd * Rr Rd Rd * K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd * ($FFh - K) Rd Rd + 1 Rd Rd - 1 Rd Rd * Rd Rd Rd Rd Rd $FF R1:R0 Rd x Rr (UU) R1:R0 Rd x Rr (SS) R1:R0 Rd x Rr (SU) R1:R0 (Rd x Rr)<<1 (UU) R1:R0 (Rd x Rr)<<1 (SS) R1:R0 (Rd x Rr)<<1 (SU) Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,C,N,V,S Z,C,N,V,S,H Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,N,V,S Z,C Z,C Z,C Z,C Z,C Z,C
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2
RJMP IJMP JMP RCALL k k k (Z) PC PC + k + 1 PC(15:0) Z PC k PC PC + k + 1
2 2 3 3
328
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
ICALL CALL RET RETI CPSE CP CPC CPI SBRC SBRS SBIC SBIS BRBS BRBC BREQ BRNE BRCS BRCC BRSH BRLO BRMI BRPL BRGE BRLT BRHS BRHC BRTS BRTC BRVS BRVC BRIE BRID Rd, Rr Rd, Rr Rd, Rr Rd, K Rr, b Rr, b A, b A, b s, k s, k k k k k k k k k k k k k k k k k k k k
(Z) b 0 b 1 I/O b 0 I/O b 1 s 1 s 0 1 0 1 0 T 1 T 0 1 0
PC(15:0) Z PC k PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b) = 0) PC PC + 2 or 3 if (Rr(b) = 1) PC PC + 2 or 3 if(I/O(A,b) = 0) PC PC + 2 or 3 If(I/O(A,b) = 1) PC PC + 2 or 3 if (SREG(s) = 1) then PC PC+k+1 if (SREG(s) = 0) then PC PC+k+1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if (I = 1) then PC PC + k + 1 if (I = 0) then PC PC + k + 1
I Z,C,N,V,S,H Z,C,N,V,S,H Z,C,N,V,S,H
3 4 4 4 1/2/3 1 1 1 1/2/3 1/2/3 1/2/3 1/2/3 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
SBI CBI A, b A, b I/O I/O I/O(A, b) 1 I/O(A, b) 0
2 2
329
2514I-AVR-10/03
LSL LSR ROL ROR ASR SWAP BSET BCLR BST BLD SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH
Rd Rd Rd Rd Rd Rd s s Rr, b Rd, b
b T T b 2 2 SREG T SREG T SREG SREG
Rd(n+1)Rd(n),Rd(0)0,CRd(7) Rd(n)Rd(n+1),Rd(7)0,CRd(0) Rd(0)C,Rd(n+1)Rd(n),CRd(7) Rd(7)C,Rd(n)Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0) Rd(7..4) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0
Z,C,N,V,H Z,C,N,V Z,C,N,V,H Z,C,N,V Z,C,N,V SREG(s) SREG(s) T C C N N Z Z I I S S V V T T H H
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
MOV MOVW LDI LD LD LD LD LD Rd, Rr Rd, Rr Rd, K Rd, X Rd, X+ Rd, -X Rd, Y Rd, Y+ Rd Rr Rd+1:Rd Rr+1:Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1
1 1 1 2 2 2 2 2
330
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
LD LDD LD LD LD LDD LDS ST ST ST ST ST ST STD ST ST ST STD STS LPM LPM LPM SPM IN OUT PUSH POP Rd, A A, Rr Rr Rd Rd, Z Rd, Z+
Rd, -Y Rd, Y+q Rd, Z Rd, Z+ Rd, -Z Rd, Z+q Rd, k X, Rr X+, Rr -X, Rr Y, Rr Y+, Rr -Y, Rr Y+q, Rr Z, Rr Z+, Rr -Z, Rr Z+q, Rr k, Rr
S I/O I/O
Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr Rd (k) R0 (Z) Rd (Z) Rd (Z), Z Z + 1 (Z) R1:R0 Rd I/O(A) I/O(A) Rr STACK Rr Rd STACK

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 1 1 2 2
MCU
NOP SLEEP WDR BREAK ( ) ( WDR )
1 1 1 N/A
331
2514I-AVR-10/03
(MHz) 1 8 16 Note: 1.8 - 5.5V 2.7 - 5.5V 4.5 - 5.5V ATmega169V-1AI ATmega169V-1MI ATmega169L-8AI ATmega169L-8MI ATmega169-16AI ATmega169-16MI 64A 64M1 64A 64M1 64A 64M1 (-40C - 85C) (-40C - 85C) (-40C - 85C)
wafer Atmel
64A 64M1 64- (1.0 mm) (TQFP) 64- pad, 9 x 9 x 1.0 mm 0.50 mm (MLF)
332
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
64A
PIN 1 B
PIN 1 IDENTIFIER
e
E1
E
D1 D C
0~7 A1 L
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 A2 D D1 E MIN - 0.05 0.95 15.75 13.90 15.75 13.90 0.30 0.09 0.45 NOM - - 1.00 16.00 14.00 16.00 14.00 - - - 0.80 TYP MAX 1.20 0.15 1.05 16.25 14.10 16.25 14.10 0.45 0.20 0.75 Note 2 Note 2 NOTE
A2
A
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AEB. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum.
E1 B C L e
10/5/2001 2325 Orchard Parkway San Jose, CA 95131 TITLE 64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) DRAWING NO. 64A REV. B
R
333
2514I-AVR-10/03
64M1
D
Marked Pin# 1 ID
E
C
TOP VIEW
SEATING PLANE
A1 A 0.08 C
L D2
Pin #1 Corner
SIDE VIEW
1 2 3
COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 b D D2 5.20 MIN 0.80 - 0.23 NOM 0.90 0.02 0.25 9.00 BSC 5.40 9.00 BSC 5.20 5.40 0.50 BSC 0.35 0.40 0.45 5.60 5.60 MAX 1.00 0.05 0.28 NOTE
E2
b
BOTTOM VIEW
e
E E2 e L
Notes: 1. JEDEC Standard MO-220, Fig. 1, VMMD.
01/15/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF) DRAWING NO. 64M1 REV. C
R
334
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
ATmega169 Rev D
* LCD * IDCODE TDI 2. LCD (>20 k) LCD 1 nF(0.47 - 1.5 nF) 1. IDCODE TDI JTAGIDCODE Update-DR1 - - ATmega169 IDCODETAPTest-Logic-Reset ID ATmega169 ID ATmega169 BYPASS ID ATmega169
-
ATmega169 Rev C
* * * * *
JTAGEN LCD LCD LCD IDCODE TDI
5. JTAGEN JTAGTDO (PF6) PF6 JTAGEN 4. LCD ( ) LCD 125 kHz (32 kHz) LCDCAP 3. LCD ( ) 1 nF "0" 1 nF 2. LCD
335
2514I-AVR-10/03
VCC VLCD -0.2V VLCD + 0.4V LCD 3 LCD 1. IDCODE TDI JTAGIDCODE Update-DR1 - - ATmega169 IDCODETAPTest-Logic-Reset ID ATmega169 ID ATmega169 BYPASS ID ATmega169
-
ATmega169 Rev B
* * * * * * *
4 MHz LCD USART ADC IDCODE TDI
7. 4 MHz 4 MHz 8 MHz. Flash/EEPROM 2 CPU EEPROM Flash rev-B CKDIV8 8 MHz ( rev. C ) 6. LCD LCD1.8V 3.1V VCC 1.8V 3.1V LCD 0.5V ( rev. C ) 5. ( rev. C ) XTAL1 4. USART
336
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
TXEN 0 USART TXEN 0 USART TXEN 0 ( rev. C ) 3. ADC ADC rev. C 2. (rev. C ) 1. IDCODE TDI JTAGIDCODE Update-DR1 - - ATmega169 IDCODETAPTest-Logic-Reset ID ATmega169 ID ATmega169 BYPASS ID ATmega169
-
337
2514I-AVR-10/03
ATmega169
Rev. 2514H-05/03 Rev. 2514I-09/03
1. " " 2. P3 Figure 2 AGND P23 Figure 11 " " 3. P37 Table 16 P39 Table 17 P41 Table 19 P67 Table 40 4. P35 "JTAG " " " JTAG " 5. P89"T/CA - TCCR0A" COM01:0COM0A1:0P128 "T/C A- TCCR2A" COM21:0 COM2A1:0 6. P218 " - TAP" JTAGEN 7. P226 JTD 8. P257 Table 119 JTAGEN 9. P286 " " 10. P336 " " JTAG IDCODE
Rev. 2514G-04/03 Rev. 2514H-05/03 Rev. 2514F-04/03 to Rev. 2514G04/03
1. Figure 145, Figure 165, Figure 192
1. ICP ICP1 2. P25 " " 3. XTAL1/XTAL2 P27" RC "
4. P31" " 5. P286 "" DCACD P37 Table 16 P41 Table 19 P287 Table 133 TBD 6. 7. P51 Figure 22 P55 Figure 25 P229 Figure 109 WRITE PINx REGISTER P67 " F " JTAG
8. P170 " - USI" / 0 0 P176 " " P177 "USI - USICR" 9. P184 " " P196 Table 88 10. P247 Figure 117 P256 Table 118
338
ATmega169V/L
2514I-AVR-10/03
ATmega169V/L
Rev. 2514D-01/03 Rev. 2514E-02/03
. P1" " ATmega169 ATmega169L
2. P2 Figure 1 , P3 Figure 2 , P5 "G (PG4..PG0)" , P69"G" P71 "I/O " PG5 3. P 256 Table 118, " ," 4. P339 "ATmega169 " " " 5. P333 " " ATmega169L 16 MHz ATmega169
Rev. 2514C-11/02 Rev. 2514D-01/03
1. P274 " JTAG " TCK 2. P283 " Flash" P284 " EEPROM" 3. P54 " " 4. P35 "JTAG " OCD 5. ADC ANA_COMP 6. P288 "SPI " P274 "SPI "
7. P250 " " Z " " " 0" 8. P212 LCDCRA " LCD " " LCD " 9. USI OUT STS LDS IN fSCKmax USI I/O I/O INOUT LDSSTS 10. P230 Table 103 TOSKONTOSCK P232 Figure 114 P233 Table 105 g10 g20 11. 4MIPS 4MHz 16 MIPS 16 MHz 12. P5 " " P6 "AVCC" A F 13. P165 " " 230.4 Mbps 230.4 kbps 14. P 165 Table 78, "UCPOL ," XCK 15. 16. P19 Table 1 RC 8,448 67,584 17. 1 18. 0 2 PWM 19. DIDR0 DIDR1
339
2514I-AVR-10/03
20. LCDDR 2 COM SEG304 21. P132 "/2" StandbyADC 22. B P285 " " 23. P250 "()" SPMEEPROM 24. ADHSM 25. P334 " "
Rev. 2514B-09/02 Rev. 2514C-11/02
1. 2. 3.
P336 " " P333 " " P334 " " 64 MLF P334 " "
Rev. 2514A-08/02 Rev. 2514B-09/02
1. Flash 10,000
340
ATmega169V/L
2514I-AVR-10/03

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